From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 20 Nov 2013 12:05:27 +0000 (+0100)
Subject: Implemented indexed part selects
X-Git-Tag: yosys-0.2.0~349
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=92035fb38ef8e7ac6319af659f7d682a047d2f70;p=yosys.git

Implemented indexed part selects
---

diff --git a/README b/README
index aa68da253..a5e3d5974 100644
--- a/README
+++ b/README
@@ -291,9 +291,6 @@ Roadmap / Large-scale TODOs
    - VlogHammer: http://www.clifford.at/yosys/vloghammer.html
    - yosys-bigsim: https://github.com/cliffordwolf/yosys-bigsim
 
-- Missing Verilog-2005 features to be implemented soon:
-  - Indexed part selects
-
 - Technology mapping for real-world applications
    - Add "mini synth script" feature to techmap pass
    - Add const-folding via cell parameters to techmap pass
diff --git a/frontends/verilog/lexer.l b/frontends/verilog/lexer.l
index fea383cf4..353f0a79b 100644
--- a/frontends/verilog/lexer.l
+++ b/frontends/verilog/lexer.l
@@ -249,6 +249,9 @@ supply1 { return TOK_SUPPLY1; }
 "<<<" { return OP_SSHL; }
 ">>>" { return OP_SSHR; }
 
+"+:" { return TOK_POS_INDEXED; }
+"-:" { return TOK_NEG_INDEXED; }
+
 "/*" { BEGIN(COMMENT); }
 <COMMENT>.    /* ignore comment body */
 <COMMENT>\n   /* ignore comment body */
diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y
index c4f386ce5..5dbf04900 100644
--- a/frontends/verilog/parser.y
+++ b/frontends/verilog/parser.y
@@ -104,6 +104,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
 %token TOK_GENERATE TOK_ENDGENERATE TOK_GENVAR
 %token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
 %token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
+%token TOK_POS_INDEXED TOK_NEG_INDEXED
 
 %type <ast> wire_type range non_opt_range expr basic_expr concat_list rvalue lvalue lvalue_concat_list
 %type <string> opt_label tok_prim_wrapper hierarchical_id
@@ -336,6 +337,16 @@ non_opt_range:
 		$$->children.push_back($2);
 		$$->children.push_back($4);
 	} |
+	'[' expr TOK_POS_INDEXED expr ']' {
+		$$ = new AstNode(AST_RANGE);
+		$$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, $2->clone(), $4), AstNode::mkconst_int(1, true)));
+		$$->children.push_back(new AstNode(AST_ADD, $2, AstNode::mkconst_int(0, true)));
+	} |
+	'[' expr TOK_NEG_INDEXED expr ']' {
+		$$ = new AstNode(AST_RANGE);
+		$$->children.push_back(new AstNode(AST_ADD, $2, AstNode::mkconst_int(0, true)));
+		$$->children.push_back(new AstNode(AST_SUB, new AstNode(AST_ADD, $2->clone(), AstNode::mkconst_int(1, true)), $4));
+	} |
 	'[' expr ']' {
 		$$ = new AstNode(AST_RANGE);
 		$$->children.push_back($2);
diff --git a/tests/simple/partsel.v b/tests/simple/partsel.v
new file mode 100644
index 000000000..acfc1ca5d
--- /dev/null
+++ b/tests/simple/partsel.v
@@ -0,0 +1,5 @@
+module test001(input [2:0] idx, input [31:0] data, output [3:0] slice_up, slice_down);
+wire [5:0] offset = idx << 2;
+assign slice_up = data[offset +: 4];
+assign slice_down = data[offset + 3 -: 4];
+endmodule