From: Andrew Waterman Date: Thu, 28 Apr 2016 22:17:28 +0000 (-0700) Subject: Add --dump-config-string flag X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9220fdfe955379af4c6cff00e7925a650b2180a5;p=riscv-isa-sim.git Add --dump-config-string flag --- diff --git a/riscv/sim.h b/riscv/sim.h index 89d3648..d8f39e2 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -29,6 +29,7 @@ public: void set_histogram(bool value); void set_procs_debug(bool value); htif_isasim_t* get_htif() { return htif.get(); } + const char* get_config_string() { return &config_string->contents()[0]; } // returns the number of processors in this simulator size_t num_cores() { return procs.size(); } diff --git a/spike_main/spike.cc b/spike_main/spike.cc index 4f8f42d..6ca7beb 100644 --- a/spike_main/spike.cc +++ b/spike_main/spike.cc @@ -17,18 +17,19 @@ static void help() { fprintf(stderr, "usage: spike [host options] [target options]\n"); fprintf(stderr, "Host Options:\n"); - fprintf(stderr, " -p Simulate processors [default 1]\n"); - fprintf(stderr, " -m Provide MiB of target memory [default 4096]\n"); - fprintf(stderr, " -d Interactive debug mode\n"); - fprintf(stderr, " -g Track histogram of PCs\n"); - fprintf(stderr, " -l Generate a log of execution\n"); - fprintf(stderr, " -h Print this help message\n"); - fprintf(stderr, " --isa= RISC-V ISA string [default %s]\n", DEFAULT_ISA); - fprintf(stderr, " --ic=:: Instantiate a cache model with S sets,\n"); - fprintf(stderr, " --dc=:: W ways, and B-byte blocks (with S and\n"); - fprintf(stderr, " --l2=:: B both powers of 2).\n"); - fprintf(stderr, " --extension= Specify RoCC Extension\n"); - fprintf(stderr, " --extlib= Shared library to load\n"); + fprintf(stderr, " -p Simulate processors [default 1]\n"); + fprintf(stderr, " -m Provide MiB of target memory [default 4096]\n"); + fprintf(stderr, " -d Interactive debug mode\n"); + fprintf(stderr, " -g Track histogram of PCs\n"); + fprintf(stderr, " -l Generate a log of execution\n"); + fprintf(stderr, " -h Print this help message\n"); + fprintf(stderr, " --isa= RISC-V ISA string [default %s]\n", DEFAULT_ISA); + fprintf(stderr, " --ic=:: Instantiate a cache model with S sets,\n"); + fprintf(stderr, " --dc=:: W ways, and B-byte blocks (with S and\n"); + fprintf(stderr, " --l2=:: B both powers of 2).\n"); + fprintf(stderr, " --extension= Specify RoCC Extension\n"); + fprintf(stderr, " --extlib= Shared library to load\n"); + fprintf(stderr, " --dump-config-string Print platform configuration string and exit\n"); exit(1); } @@ -37,6 +38,7 @@ int main(int argc, char** argv) bool debug = false; bool histogram = false; bool log = false; + bool dump_config_string = false; size_t nprocs = 1; size_t mem_mb = 0; std::unique_ptr ic; @@ -58,6 +60,7 @@ int main(int argc, char** argv) parser.option(0, "l2", 1, [&](const char* s){l2.reset(cache_sim_t::construct(s, "L2$"));}); parser.option(0, "isa", 1, [&](const char* s){isa = s;}); parser.option(0, "extension", 1, [&](const char* s){extension = find_extension(s);}); + parser.option(0, "dump-config-string", 0, [&](const char *s){dump_config_string = true;}); parser.option(0, "extlib", 1, [&](const char *s){ void *lib = dlopen(s, RTLD_NOW | RTLD_GLOBAL); if (lib == NULL) { @@ -67,11 +70,17 @@ int main(int argc, char** argv) }); auto argv1 = parser.parse(argv); - if (!*argv1) - help(); std::vector htif_args(argv1, (const char*const*)argv + argc); sim_t s(isa, nprocs, mem_mb, htif_args); + if (dump_config_string) { + printf("%s", s.get_config_string()); + return 0; + } + + if (!*argv1) + help(); + if (ic && l2) ic->set_miss_handler(&*l2); if (dc && l2) dc->set_miss_handler(&*l2); for (size_t i = 0; i < nprocs; i++)