From: Nilay Vaish <nilay@cs.wisc.edu>
Date: Mon, 20 Oct 2014 21:47:55 +0000 (-0500)
Subject: cpu: o3: corrects base FP and CC register index in removeThread()
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=922a9d8ed2488a3483dbbfff47a4f341fb707b7b;p=gem5.git

cpu: o3: corrects base FP and CC register index in removeThread()
---

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 6895355f0..fd51cd123 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -835,26 +835,22 @@ FullO3CPU<Impl>::removeThread(ThreadID tid)
     // Unbind Int Regs from Rename Map
     for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
         PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
-
         scoreboard.unsetReg(phys_reg);
         freeList.addReg(phys_reg);
     }
 
     // Unbind Float Regs from Rename Map
-    int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
-    for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) {
+    int max_reg = TheISA::FP_Reg_Base + TheISA::NumFloatRegs;
+    for (int freg = TheISA::FP_Reg_Base; freg < max_reg; freg++) {
         PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
-
         scoreboard.unsetReg(phys_reg);
         freeList.addReg(phys_reg);
     }
 
     // Unbind condition-code Regs from Rename Map
-    max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs;
-    for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
-         creg < max_reg; creg++) {
+    max_reg = TheISA::CC_Reg_Base + TheISA::NumCCRegs;
+    for (int creg = TheISA::CC_Reg_Base; creg < max_reg; creg++) {
         PhysRegIndex phys_reg = renameMap[tid].lookup(creg);
-
         scoreboard.unsetReg(phys_reg);
         freeList.addReg(phys_reg);
     }