From: Cesar Strauss <cestrauss@gmail.com>
Date: Tue, 7 Jul 2020 09:30:02 +0000 (-0300)
Subject: Clear input data along with valid_i
X-Git-Tag: div_pipeline~162^2~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9231efba4ccc77557b6c5884f379aee20fd403c7;p=soc.git

Clear input data along with valid_i
---

diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py
index 828511b6..c1ca6fa3 100644
--- a/src/soc/experiment/alu_hier.py
+++ b/src/soc/experiment/alu_hier.py
@@ -400,6 +400,10 @@ def run_op(dut, a, b, op, inv_a=0):
         yield
 
     yield dut.p.valid_i.eq(0)
+    yield dut.a.eq(0)
+    yield dut.b.eq(0)
+    yield dut.op.insn_type.eq(0)
+    yield dut.op.invert_a.eq(0)
 
     # wait for the ALU to present the output data
     while not (yield dut.n.valid_o):