From: Gabe Black Date: Mon, 25 Jan 2021 06:15:06 +0000 (-0800) Subject: cpu: Style fixes in cpu/exec_context.hh and thread_context.hh. X-Git-Tag: develop-gem5-snapshot~207 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=92489797d471b59f2d55c704ec2e8e8a6cd4cc5d;p=gem5.git cpu: Style fixes in cpu/exec_context.hh and thread_context.hh. Change-Id: I2eb82cc6f6ba29c1df74e53b78b57c1a65577837 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39659 Reviewed-by: Daniel Carvalho Reviewed-by: Bobby R. Bruce Maintainer: Bobby R. Bruce Tested-by: kokoro --- diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh index c0b8dcd2f..42dafbcac 100644 --- a/src/cpu/exec_context.hh +++ b/src/cpu/exec_context.hh @@ -105,36 +105,35 @@ class ExecContext /** Vector Register Interfaces. */ /** @{ */ /** Reads source vector register operand. */ - virtual const TheISA::VecRegContainer& - readVecRegOperand(const StaticInst *si, int idx) const = 0; + virtual const TheISA::VecRegContainer& readVecRegOperand( + const StaticInst *si, int idx) const = 0; /** Gets destination vector register operand for modification. */ - virtual TheISA::VecRegContainer& - getWritableVecRegOperand(const StaticInst *si, int idx) = 0; + virtual TheISA::VecRegContainer& getWritableVecRegOperand( + const StaticInst *si, int idx) = 0; /** Sets a destination vector register operand to a value. */ - virtual void - setVecRegOperand(const StaticInst *si, int idx, - const TheISA::VecRegContainer& val) = 0; + virtual void setVecRegOperand(const StaticInst *si, int idx, + const TheISA::VecRegContainer& val) = 0; /** @} */ /** Vector Register Lane Interfaces. */ /** @{ */ /** Reads source vector 8bit operand. */ - virtual ConstVecLane8 - readVec8BitLaneOperand(const StaticInst *si, int idx) const = 0; + virtual ConstVecLane8 readVec8BitLaneOperand( + const StaticInst *si, int idx) const = 0; /** Reads source vector 16bit operand. */ - virtual ConstVecLane16 - readVec16BitLaneOperand(const StaticInst *si, int idx) const = 0; + virtual ConstVecLane16 readVec16BitLaneOperand( + const StaticInst *si, int idx) const = 0; /** Reads source vector 32bit operand. */ - virtual ConstVecLane32 - readVec32BitLaneOperand(const StaticInst *si, int idx) const = 0; + virtual ConstVecLane32 readVec32BitLaneOperand( + const StaticInst *si, int idx) const = 0; /** Reads source vector 64bit operand. */ - virtual ConstVecLane64 - readVec64BitLaneOperand(const StaticInst *si, int idx) const = 0; + virtual ConstVecLane64 readVec64BitLaneOperand( + const StaticInst *si, int idx) const = 0; /** Write a lane of the destination vector operand. */ /** @{ */ @@ -225,9 +224,9 @@ class ExecContext * mode need not override (though in that case this function * should never be called). */ - virtual Fault readMem(Addr addr, uint8_t *data, unsigned int size, - Request::Flags flags, - const std::vector& byte_enable) + virtual Fault + readMem(Addr addr, uint8_t *data, unsigned int size, + Request::Flags flags, const std::vector& byte_enable) { panic("ExecContext::readMem() should be overridden\n"); } @@ -239,9 +238,9 @@ class ExecContext * mode need not override (though in that case this function * should never be called). */ - virtual Fault initiateMemRead(Addr addr, unsigned int size, - Request::Flags flags, - const std::vector& byte_enable) + virtual Fault + initiateMemRead(Addr addr, unsigned int size, + Request::Flags flags, const std::vector& byte_enable) { panic("ExecContext::initiateMemRead() should be overridden\n"); } @@ -263,9 +262,9 @@ class ExecContext * For atomic-mode contexts, perform an atomic AMO (a.k.a., Atomic * Read-Modify-Write Memory Operation) */ - virtual Fault amoMem(Addr addr, uint8_t *data, unsigned int size, - Request::Flags flags, - AtomicOpFunctorPtr amo_op) + virtual Fault + amoMem(Addr addr, uint8_t *data, unsigned int size, + Request::Flags flags, AtomicOpFunctorPtr amo_op) { panic("ExecContext::amoMem() should be overridden\n"); } @@ -274,9 +273,9 @@ class ExecContext * For timing-mode contexts, initiate an atomic AMO (atomic * read-modify-write memory operation) */ - virtual Fault initiateMemAMO(Addr addr, unsigned int size, - Request::Flags flags, - AtomicOpFunctorPtr amo_op) + virtual Fault + initiateMemAMO(Addr addr, unsigned int size, Request::Flags flags, + AtomicOpFunctorPtr amo_op) { panic("ExecContext::initiateMemAMO() should be overridden\n"); } diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index 772a78039..874146a55 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -94,10 +94,7 @@ class ThreadContext : public PCEventScope bool getUseForClone() { return useForClone; } - void setUseForClone(bool newUseForClone) - { - useForClone = newUseForClone; - } + void setUseForClone(bool new_val) { useForClone = new_val; } enum Status { @@ -288,7 +285,7 @@ class ThreadContext : public PCEventScope virtual void setMiscReg(RegIndex misc_reg, RegVal val) = 0; - virtual RegId flattenRegId(const RegId& regId) const = 0; + virtual RegId flattenRegId(const RegId& reg_id) const = 0; // Also not necessarily the best location for these two. Hopefully will go // away once we decide upon where st cond failures goes. @@ -332,8 +329,8 @@ class ThreadContext : public PCEventScope const TheISA::VecRegContainer& val) = 0; virtual const TheISA::VecElem& readVecElemFlat(RegIndex idx, - const ElemIndex& elemIdx) const = 0; - virtual void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx, + const ElemIndex& elem_idx) const = 0; + virtual void setVecElemFlat(RegIndex idx, const ElemIndex& elem_idx, const TheISA::VecElem& val) = 0; virtual const TheISA::VecPredRegContainer &