From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 15 May 2023 19:38:34 +0000 (+0100)
Subject: RC1 does not exist in CROps, the selection of behaviour *called* RC1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=924d00489e6521794773a47235865fab5fc0c3d8;p=openpower-isa.git

RC1 does not exist in CROps, the selection of behaviour *called* RC1
is whether the CROp destination is a 3-bit CR *field* (RC1=0)
or if it is a 5-bit CR *bit* (RC1=1)
---

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index ab1ead61..9774b6c4 100644
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -2332,8 +2332,8 @@ class CROpMRRM(MRBaseRM, ZZCombinedBaseRM, CROpBaseRM):
 
 class CROpFF3RM(FFRc0BaseRM, PredicateBaseRM, VLiBaseRM, DZBaseRM, SZBaseRM, CROpBaseRM):
     """crop: ffirst 3-bit mode"""
-    RC1: BaseRM[19]
-    VLi: BaseRM[20]
+    VLi: BaseRM[19]
+    RC1 = 0
     inv: BaseRM[21]
     dz: BaseRM[22]
     sz: BaseRM[23]
@@ -2347,6 +2347,7 @@ class CROpFF3RM(FFRc0BaseRM, PredicateBaseRM, VLiBaseRM, DZBaseRM, SZBaseRM, CRO
 # Please revisit this code; there is an inactive sketch below.
 class CROpFF5RM(FFRc1BaseRM, PredicateBaseRM, VLiBaseRM, CROpBaseRM):
     """cr_op: ffirst 5-bit mode"""
+    RC1 = 1 # temporary hack
     VLi: BaseRM[19]
     inv: BaseRM[21]
     CR: BaseRM[22, 23]