From: Jacob Lifshay Date: Thu, 4 May 2023 04:27:06 +0000 (-0700) Subject: add fcvt/fmv -- no tests yet X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9255849db0fa7b5aa703d1bde0ee7257579ffb21;p=openpower-isa.git add fcvt/fmv -- no tests yet --- diff --git a/openpower/isa/fpcvt.mdwn b/openpower/isa/fpcvt.mdwn index c5a955f9..75e13f38 100644 --- a/openpower/isa/fpcvt.mdwn +++ b/openpower/isa/fpcvt.mdwn @@ -18,3 +18,301 @@ Special Registers Altered: FPRF FR FI FX XX CR1 (if Rc=1) + +# [DRAFT] Floating Convert From Integer In GPR + +X-Form + +* fcvtfg FRT,RB,IT (Rc=0) +* fcvtfg. FRT,RB,IT (Rc=1) + +Pseudo-code: + + if IT[0] = 0 then # 32-bit int -> 64-bit float + # rounding never necessary, so don't touch FPSCR + # based off xvcvsxwdp + if IT = 0 then # Signed 32-bit + src <- bfp_CONVERT_FROM_SI32((RB)[32:63]) + else # IT = 1 -- Unsigned 32-bit + src <- bfp_CONVERT_FROM_UI32((RB)[32:63]) + FRT <- bfp64_CONVERT_FROM_BFP(src) + else + # rounding may be necessary. based off xscvuxdsp + reset_xflags() + switch(IT) + case(0): # Signed 32-bit + src <- bfp_CONVERT_FROM_SI32((RB)[32:63]) + case(1): # Unsigned 32-bit + src <- bfp_CONVERT_FROM_UI32((RB)[32:63]) + case(2): # Signed 64-bit + src <- bfp_CONVERT_FROM_SI64((RB)) + default: # Unsigned 64-bit + src <- bfp_CONVERT_FROM_UI64((RB)) + rnd <- bfp_ROUND_TO_BFP64(FPSCR[RN], src) + result <- bfp64_CONVERT_FROM_BFP(rnd) + cls <- fprf_CLASS_BFP64(result) + if xx_flag = 1 then SetFX(FPSCR[XX]) + FRT <- result + FPSCR[FPRF] <- cls + FPSCR[FR] <- inc_flag + FPSCR[FI] <- xx_flag + +Special Registers Altered: + + CR1 (if Rc=1) + FPRF FR FI FX XX (if IT[0]=1) + +# [DRAFT] Floating Convert From Integer In GPR Single + +X-Form + +* fcvtfgs FRT,RB,IT (Rc=0) +* fcvtfgs. FRT,RB,IT (Rc=1) + +Pseudo-code: + + + + # rounding may be necessary. based off xscvuxdsp + reset_xflags() + switch(IT) + case(0): # Signed 32-bit + src <- bfp_CONVERT_FROM_SI32((RB)[32:63]) + case(1): # Unsigned 32-bit + src <- bfp_CONVERT_FROM_UI32((RB)[32:63]) + case(2): # Signed 64-bit + src <- bfp_CONVERT_FROM_SI64((RB)) + default: # Unsigned 64-bit + src <- bfp_CONVERT_FROM_UI64((RB)) + rnd <- bfp_ROUND_TO_BFP32(FPSCR[RN], src) + result32 <- bfp32_CONVERT_FROM_BFP(rnd) + cls <- fprf_CLASS_BFP32(result32) + result <- DOUBLE(result32) + if xx_flag = 1 then SetFX(FPSCR[XX]) + FRT <- result + FPSCR[FPRF] <- cls + FPSCR[FR] <- inc_flag + FPSCR[FI] <- xx_flag + +Special Registers Altered: + + CR1 (if Rc=1) + FPRF FR FI FX XX + +# [DRAFT] Floating Convert To Integer In GPR + +XO-Form + +* fcvttg RT,FRB,CVM,IT (OE=0 Rc=0) +* fcvttg. RT,FRB,CVM,IT (OE=0 Rc=1) +* fcvttgo RT,FRB,CVM,IT (OE=1 Rc=0) +* fcvttgo. RT,FRB,CVM,IT (OE=1 Rc=1) + +Pseudo-code: + + # based on xscvdpuxws + reset_xflags() + src <- bfp_CONVERT_FROM_BFP64((FRB)) + switch(IT) + case(0): # Signed 32-bit + range_min <- bfp_CONVERT_FROM_SI32(0x8000_0000) + range_max <- bfp_CONVERT_FROM_SI32(0x7FFF_FFFF) + js_mask <- 0xFFFF_FFFF + case(1): # Unsigned 32-bit + range_min <- bfp_CONVERT_FROM_UI32(0) + range_max <- bfp_CONVERT_FROM_UI32(0xFFFF_FFFF) + js_mask <- 0xFFFF_FFFF + case(2): # Signed 64-bit + range_min <- bfp_CONVERT_FROM_SI64(-0x8000_0000_0000_0000) + range_max <- bfp_CONVERT_FROM_SI64(0x7FFF_FFFF_FFFF_FFFF) + js_mask <- 0xFFFF_FFFF_FFFF_FFFF + default: # Unsigned 64-bit + range_min <- bfp_CONVERT_FROM_UI64(0) + range_max <- bfp_CONVERT_FROM_UI64(0xFFFF_FFFF_FFFF_FFFF) + js_mask <- 0xFFFF_FFFF_FFFF_FFFF + if (CVM[2] = 1) | (FPSCR[RN] = 0b01) then + rnd <- bfp_ROUND_TO_INTEGER_TRUNC(src) + else if FPSCR[RN] = 0b00 then + rnd <- bfp_ROUND_TO_INTEGER_NEAR_EVEN(src) + else if FPSCR[RN] = 0b10 then + rnd <- bfp_ROUND_TO_INTEGER_CEIL(src) + else if FPSCR[RN] = 0b11 then + rnd <- bfp_ROUND_TO_INTEGER_FLOOR(src) + switch(CVM) + case(0, 1): # OpenPower semantics + if IsNaN(rnd) then + result <- si64_CONVERT_FROM_BFP(range_min) + else if bfp_COMPARE_GT(rnd, range_max) then + result <- ui64_CONVERT_FROM_BFP(range_max) + else if bfp_COMPARE_LT(rnd, range_min) then + result <- si64_CONVERT_FROM_BFP(range_min) + else if IT[1] = 1 then # Unsigned 32/64-bit + result <- ui64_CONVERT_FROM_BFP(range_max) + else # Signed 32/64-bit + result <- si64_CONVERT_FROM_BFP(range_max) + case(2, 3): # Java/Saturating semantics + if IsNaN(rnd) then + result <- [0] * 64 + else if bfp_COMPARE_GT(rnd, range_max) then + result <- ui64_CONVERT_FROM_BFP(range_max) + else if bfp_COMPARE_LT(rnd, range_min) then + result <- si64_CONVERT_FROM_BFP(range_min) + else if IT[1] = 1 then # Unsigned 32/64-bit + result <- ui64_CONVERT_FROM_BFP(range_max) + else # Signed 32/64-bit + result <- si64_CONVERT_FROM_BFP(range_max) + default: # JavaScript semantics + # CVM = 6, 7 are illegal instructions + # this works because the largest type we try to convert from has + # 53 significand bits, and the largest type we try to convert to + # has 64 bits, and the sum of those is strictly less than the 128 + # bits of the intermediate result. + limit <- bfp_CONVERT_FROM_UI128([1] * 128) + if IsInf(rnd) | IsNaN(rnd) then + result <- [0] * 64 + else if bfp_COMPARE_GT(bfp_ABSOLUTE(rnd), limit) then + result <- [0] * 64 + else + result128 <- si128_CONVERT_FROM_BFP(rnd) + result <- result128[64:127] & js_mask + switch(IT) + case(0): # Signed 32-bit + result <- EXTS64(result[32:63]) + result_bfp <- bfp_CONVERT_FROM_SI32(result[32:63]) + case(1): # Unsigned 32-bit + result <- EXTZ64(result[32:63]) + result_bfp <- bfp_CONVERT_FROM_UI32(result[32:63]) + case(2): # Signed 64-bit + result_bfp <- bfp_CONVERT_FROM_SI64(result) + default: # Unsigned 64-bit + result_bfp <- bfp_CONVERT_FROM_UI64(result) + if vxsnan_flag = 1 then SetFX(FPSCR[VXSNAN]) + if vxcvi_flag = 1 then SetFX(FPSCR[VXCVI]) + if xx_flag = 1 then SetFX(FPSCR[XX]) + vx_flag <- vxsnan_flag | vxcvi_flag + vex_flag <- FPSCR[VE] & vx_flag + if vex_flag = 0 then + RT <- result + FPSCR[FPRF] <- undefined + FPSCR[FR] <- inc_flag + FPSCR[FI] <- xx_flag + if IsNaN(src) | ¬bfp_COMPARE_EQ(src, result_bfp) then + overflow <- 1 # signals SO only when OE = 1 + else + FPSCR[FR] <- 0 + FPSCR[FI] <- 0 + +Special Registers Altered: + + CR0 (if Rc=1) + SO OV OV32 (if OE=1) + FPRF=0bUUUUU FR FI FX XX VXSNAN VXCV + +# [DRAFT] Floating Convert To Integer In GPR Single + +XO-Form + +* fcvttgs RT,FRB,CVM,IT (OE=0 Rc=0) +* fcvttgs. RT,FRB,CVM,IT (OE=0 Rc=1) +* fcvttgso RT,FRB,CVM,IT (OE=1 Rc=0) +* fcvttgso. RT,FRB,CVM,IT (OE=1 Rc=1) + +Pseudo-code: + + # based on xscvdpuxws + reset_xflags() + src <- bfp_CONVERT_FROM_BFP32(SINGLE((FRB))) + switch(IT) + case(0): # Signed 32-bit + range_min <- bfp_CONVERT_FROM_SI32(0x8000_0000) + range_max <- bfp_CONVERT_FROM_SI32(0x7FFF_FFFF) + js_mask <- 0xFFFF_FFFF + case(1): # Unsigned 32-bit + range_min <- bfp_CONVERT_FROM_UI32(0) + range_max <- bfp_CONVERT_FROM_UI32(0xFFFF_FFFF) + js_mask <- 0xFFFF_FFFF + case(2): # Signed 64-bit + range_min <- bfp_CONVERT_FROM_SI64(-0x8000_0000_0000_0000) + range_max <- bfp_CONVERT_FROM_SI64(0x7FFF_FFFF_FFFF_FFFF) + js_mask <- 0xFFFF_FFFF_FFFF_FFFF + default: # Unsigned 64-bit + range_min <- bfp_CONVERT_FROM_UI64(0) + range_max <- bfp_CONVERT_FROM_UI64(0xFFFF_FFFF_FFFF_FFFF) + js_mask <- 0xFFFF_FFFF_FFFF_FFFF + if (CVM[2] = 1) | (FPSCR[RN] = 0b01) then + rnd <- bfp_ROUND_TO_INTEGER_TRUNC(src) + else if FPSCR[RN] = 0b00 then + rnd <- bfp_ROUND_TO_INTEGER_NEAR_EVEN(src) + else if FPSCR[RN] = 0b10 then + rnd <- bfp_ROUND_TO_INTEGER_CEIL(src) + else if FPSCR[RN] = 0b11 then + rnd <- bfp_ROUND_TO_INTEGER_FLOOR(src) + switch(CVM) + case(0, 1): # OpenPower semantics + if IsNaN(rnd) then + result <- si64_CONVERT_FROM_BFP(range_min) + else if bfp_COMPARE_GT(rnd, range_max) then + result <- ui64_CONVERT_FROM_BFP(range_max) + else if bfp_COMPARE_LT(rnd, range_min) then + result <- si64_CONVERT_FROM_BFP(range_min) + else if IT[1] = 1 then # Unsigned 32/64-bit + result <- ui64_CONVERT_FROM_BFP(range_max) + else # Signed 32/64-bit + result <- si64_CONVERT_FROM_BFP(range_max) + case(2, 3): # Java/Saturating semantics + if IsNaN(rnd) then + result <- [0] * 64 + else if bfp_COMPARE_GT(rnd, range_max) then + result <- ui64_CONVERT_FROM_BFP(range_max) + else if bfp_COMPARE_LT(rnd, range_min) then + result <- si64_CONVERT_FROM_BFP(range_min) + else if IT[1] = 1 then # Unsigned 32/64-bit + result <- ui64_CONVERT_FROM_BFP(range_max) + else # Signed 32/64-bit + result <- si64_CONVERT_FROM_BFP(range_max) + default: # JavaScript semantics + # CVM = 6, 7 are illegal instructions + # this works because the largest type we try to convert from has + # 53 significand bits, and the largest type we try to convert to + # has 64 bits, and the sum of those is strictly less than the 128 + # bits of the intermediate result. + limit <- bfp_CONVERT_FROM_UI128([1] * 128) + if IsInf(rnd) | IsNaN(rnd) then + result <- [0] * 64 + else if bfp_COMPARE_GT(bfp_ABSOLUTE(rnd), limit) then + result <- [0] * 64 + else + result128 <- si128_CONVERT_FROM_BFP(rnd) + result <- result128[64:127] & js_mask + switch(IT) + case(0): # Signed 32-bit + result <- EXTS64(result[32:63]) + result_bfp <- bfp_CONVERT_FROM_SI32(result[32:63]) + case(1): # Unsigned 32-bit + result <- EXTZ64(result[32:63]) + result_bfp <- bfp_CONVERT_FROM_UI32(result[32:63]) + case(2): # Signed 64-bit + result_bfp <- bfp_CONVERT_FROM_SI64(result) + default: # Unsigned 64-bit + result_bfp <- bfp_CONVERT_FROM_UI64(result) + if vxsnan_flag = 1 then SetFX(FPSCR[VXSNAN]) + if vxcvi_flag = 1 then SetFX(FPSCR[VXCVI]) + if xx_flag = 1 then SetFX(FPSCR[XX]) + vx_flag <- vxsnan_flag | vxcvi_flag + vex_flag <- FPSCR[VE] & vx_flag + if vex_flag = 0 then + RT <- result + FPSCR[FPRF] <- undefined + FPSCR[FR] <- inc_flag + FPSCR[FI] <- xx_flag + if IsNaN(src) | ¬bfp_COMPARE_EQ(src, result_bfp) then + overflow <- 1 # signals SO only when OE = 1 + else + FPSCR[FR] <- 0 + FPSCR[FI] <- 0 + +Special Registers Altered: + + CR0 (if Rc=1) + SO OV OV32 (if OE=1) + FPRF=0bUUUUU FR FI FX XX VXSNAN VXCV diff --git a/openpower/isa/fpmove.mdwn b/openpower/isa/fpmove.mdwn index e1d95348..179119cf 100644 --- a/openpower/isa/fpmove.mdwn +++ b/openpower/isa/fpmove.mdwn @@ -76,3 +76,63 @@ Pseudo-code: Special Registers Altered: CR1 (if Rc=1) + +# [DRAFT] Floating Move To GPR + +X-Form + +* fmvtg RT,FRB (Rc=0) +* fmvtg. RT,FRB (Rc=1) + +Pseudo-code: + + RT <- (FRB) + +Special Registers Altered: + + CR0 (if Rc=1) + +# [DRAFT] Floating Move To GPR Single + +X-Form + +* fmvtgs RT,FRB (Rc=0) +* fmvtgs. RT,FRB (Rc=1) + +Pseudo-code: + + RT <- [0] * (XLEN/2) || SINGLE((FRB)) # SINGLE since that's what stfs uses + +Special Registers Altered: + + CR0 (if Rc=1) + +# [DRAFT] Floating Move From GPR + +X-Form + +* fmvfg FRT,RB (Rc=0) +* fmvfg. FRT,RB (Rc=1) + +Pseudo-code: + + FRT <- (RB) + +Special Registers Altered: + + CR1 (if Rc=1) + +# [DRAFT] Floating Move From GPR Single + +X-Form + +* fmvfgs FRT,RB (Rc=0) +* fmvfgs. FRT,RB (Rc=1) + +Pseudo-code: + + FRT <- DOUBLE((RB)[XLEN/2:XLEN-1]) # DOUBLE since that's what lfs uses + +Special Registers Altered: + + CR1 (if Rc=1) diff --git a/openpower/isatables/RM-2P-1S1D.csv b/openpower/isatables/RM-2P-1S1D.csv index b37785ff..4d3a0cca 100644 --- a/openpower/isatables/RM-2P-1S1D.csv +++ b/openpower/isatables/RM-2P-1S1D.csv @@ -41,6 +41,7 @@ extsw,NORMAL,,2P,EXTRA3,EN,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0 fsqrts,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 fres,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 frsqrtes,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 +fcvttgs,NORMAL,,2P,EXTRA3,EN,TODO,0,0,0,0,FRB,0,RT,0,CR0,0 fcbrts,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 fsinpis,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 fasinpis,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 @@ -64,6 +65,10 @@ facoshs,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 fatanhs,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 fexp2m1s,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 flog2p1s,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 +fcvttgso,NORMAL,,2P,EXTRA3,EN,TODO,0,0,0,0,FRB,0,RT,0,CR0,0 +fmvtgs,NORMAL,,2P,EXTRA3,EN,TODO,0,0,0,0,FRB,0,RT,0,CR0,0 +fcvtfgs,NORMAL,,2P,EXTRA3,EN,TODO,0,0,0,0,RB,0,FRT,0,CR1,0 +fmvfgs,NORMAL,,2P,EXTRA3,EN,TODO,0,0,0,0,RB,0,FRT,0,CR1,0 fexpm1s,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 flogp1s,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 fexp10m1s,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 @@ -88,6 +93,7 @@ frsqrte,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 4/14=fctiwu,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 4/15=fctiwuz,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 8/8=fabs,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 +fcvttg,NORMAL,,2P,EXTRA3,EN,TODO,0,0,0,0,FRB,0,RT,0,CR0,0 12/8=frin,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 13/8=friz,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 14/8=frip,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 @@ -116,6 +122,10 @@ facosh,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 fatanh,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 fexp2m1,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 flog2p1,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 +fcvttgo,NORMAL,,2P,EXTRA3,EN,TODO,0,0,0,0,FRB,0,RT,0,CR0,0 +fmvtg,NORMAL,,2P,EXTRA3,EN,TODO,0,0,0,0,FRB,0,RT,0,CR0,0 +fcvtfg,NORMAL,,2P,EXTRA3,EN,TODO,0,0,0,0,RB,0,FRT,0,CR1,0 +fmvfg,NORMAL,,2P,EXTRA3,EN,TODO,0,0,0,0,RB,0,FRT,0,CR1,0 fexpm1,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 flogp1,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 25/14=fctid,NORMAL,,2P,EXTRA3,EN,d:FRT;d:CR1,s:FRB,0,0,0,FRB,0,FRT,0,CR1,0 diff --git a/openpower/isatables/minor_59.csv b/openpower/isatables/minor_59.csv index 1df79976..adb2822d 100644 --- a/openpower/isatables/minor_59.csv +++ b/openpower/isatables/minor_59.csv @@ -80,3 +80,8 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou # 1111101111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxmagcs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg 1101001111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmods,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg 1111001111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fremainders,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +0100001110,FPU,OP_FPOP,NONE,FRB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fcvttgs,XO,,1,unofficial until submitted and approved/renumbered by the opf isa wg +1100001110,FPU,OP_FPOP,NONE,FRB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fcvttgso,XO,,1,unofficial until submitted and approved/renumbered by the opf isa wg +1100001110,FPU,OP_FPOP,NONE,FRB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,fmvtgs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +1100001111,FPU,OP_FPOP,NONE,RB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,fcvtfgs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +1100001111,FPU,OP_FPOP,NONE,RB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,fmvfgs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg diff --git a/openpower/isatables/minor_63.csv b/openpower/isatables/minor_63.csv index 0067705d..c1e4031b 100644 --- a/openpower/isatables/minor_63.csv +++ b/openpower/isatables/minor_63.csv @@ -105,3 +105,8 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou # 1111101111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxmagc,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg 1101001111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmod,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg 1111001111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fremainder,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +0100001110,FPU,OP_FPOP,NONE,FRB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fcvttg,XO,,1,unofficial until submitted and approved/renumbered by the opf isa wg +1100001110,FPU,OP_FPOP,NONE,FRB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,fcvttgo,XO,,1,unofficial until submitted and approved/renumbered by the opf isa wg +1100001110,FPU,OP_FPOP,NONE,FRB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,fmvtg,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +1100001111,FPU,OP_FPOP,NONE,RB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,fcvtfg,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +1100001111,FPU,OP_FPOP,NONE,RB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC_ONLY,0,0,fmvfg,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index 2e6b6427..f7d7bbe9 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -1916,6 +1916,10 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop): 'fmvis', 'fishmv', 'pcdec', "maddedu", "divmod2du", "dsld", "dsrd", "maddedus", "shadd", "shaddw", "shadduw", + "fcvttg", "fcvttgo", "fcvttgs", "fcvttgso", + "fmvtg", "fmvtgs", + "fcvtfg", "fcvtfgs", + "fmvfg", "fmvfgs", ]: illegal = False ins_name = dotstrp diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py index e8406ccc..b9ddb31a 100644 --- a/src/openpower/decoder/power_enums.py +++ b/src/openpower/decoder/power_enums.py @@ -733,6 +733,10 @@ _insns = [ "fmr", "fabs", "fnabs", "fneg", "fcpsgn", # FP move/abs/neg "fmvis", # FP load immediate "fishmv", # Float Replace Lower-Half Single, Immediate + "fcvttg", "fcvttgo", "fcvttgs", "fcvttgso", + "fmvtg", "fmvtgs", + "fcvtfg", "fcvtfgs", + "fmvfg", "fmvfgs", 'grev', 'grev.', 'grevi', 'grevi.', 'grevw', 'grevw.', 'grevwi', 'grevwi.', "hrfid", "icbi", "icbt", "isel", "isync",