From: Cesar Strauss <cestrauss@gmail.com>
Date: Sun, 1 Jan 2023 12:32:54 +0000 (-0300)
Subject: Handle newer nMigen adding a "bench" top-level root in VCD files
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=92608b733473f15c6fee7e1d12c5b3a4117bc821;p=openpower-isa.git

Handle newer nMigen adding a "bench" top-level root in VCD files
---

diff --git a/src/openpower/test/runner.py b/src/openpower/test/runner.py
index cf9b28b3..4068d1ab 100644
--- a/src/openpower/test/runner.py
+++ b/src/openpower/test/runner.py
@@ -534,7 +534,7 @@ class TestRunnerBase(FHDLTestCase):
 
         write_gtkw("%s.gtkw" % gtkname,
                    "%s.vcd" % gtkname,
-                   traces, styles, module='top.issuer')
+                   traces, styles, module='bench.top.issuer')
 
         # add run of instructions
         sim.add_sync_process(process)