From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 30 Apr 2019 13:19:04 +0000 (+0200)
Subject: Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970
X-Git-Tag: yosys-0.9~142^2~13
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9268cd16135db87920ee49a54a16dab62fc1f4a8;p=yosys.git

Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 7e1159cac..dd6817873 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -3456,7 +3456,7 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
 	pack();
 	other.pack();
 
-	if (chunks_.size() != chunks_.size())
+	if (chunks_.size() != other.chunks_.size())
 		return false;
 
 	updhash();