From: yimmanuel3@f4ac60d763911c3fa518755176e4b9ed455c75d8 <yimmanuel3@web>
Date: Sun, 2 Feb 2020 09:05:24 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~3615
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=926c74cb254893669944ba89496072be1a768192;p=libreriscv.git

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diff --git a/index.mdwn b/index.mdwn
index fb76a30ed..75100710e 100644
--- a/index.mdwn
+++ b/index.mdwn
@@ -21,7 +21,7 @@ regularly exploit.
 
 But beyond the contemporary ever increasing cry for privacy, is a very real need for reliable safety critical processors.
 LibreSOC poses to you that it is impossible to trust a processor in a safety critical environment without both access
-to that processor's source and a cycle accurate HDL simulator that guarantees developer's their code behaves as they 
+to that processor's source and a cycle accurate HDL simulator that guarantees developers their code behaves as they 
 expect. An ISA level simulator is no longer satisfactory.
 
 Refer to this [paper](https://ieeexplore.ieee.org/document/4519604) authored by Cyberphysical System expert Ed-Lee for more details.