From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 18 Jul 2019 13:31:27 +0000 (+0200)
Subject: Merge pull request #1203 from whitequark/write_verilog-zero-width-values
X-Git-Tag: working-ls180~1186
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=927f0caa9d70ccf3634b29d8558c78febcc9081c;p=yosys.git

Merge pull request #1203 from whitequark/write_verilog-zero-width-values

write_verilog: dump zero width constants correctly
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927f0caa9d70ccf3634b29d8558c78febcc9081c