From: Dmitry Selyutin Date: Sun, 18 Sep 2022 16:05:42 +0000 (+0300) Subject: test_pysvp64dis: test RC1/~RC1 in ff/pr X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9290138fdb69fb274253e640b7c2ae5000492813;p=openpower-isa.git test_pysvp64dis: test RC1/~RC1 in ff/pr --- diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py index 40ef39a5..97df1c51 100644 --- a/src/openpower/sv/trans/test_pysvp64dis.py +++ b/src/openpower/sv/trans/test_pysvp64dis.py @@ -213,6 +213,14 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) + def test_13_RC1(self): + expected = [ + "sv.add/ff=RC1 *3,*7,*11", + "sv.add/pr=RC1 *3,*7,*11", + "sv.add/ff=~RC1 *3,*7,*11", + "sv.add/pr=~RC1 *3,*7,*11", + ] + if __name__ == "__main__": unittest.main()