From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 10 Feb 2015 15:01:40 +0000 (+0100)
Subject: phy: add hw_init_reset (useful when used without CPU)
X-Git-Tag: 24jan2021_ls180~2604^2~44
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=92904330f7bbeb8dbdc3ff95ea372018832446a1;p=litex.git

phy: add hw_init_reset (useful when used without CPU)
---

diff --git a/liteeth/phy/gmii.py b/liteeth/phy/gmii.py
index 477ca359..1388704b 100644
--- a/liteeth/phy/gmii.py
+++ b/liteeth/phy/gmii.py
@@ -34,7 +34,7 @@ class LiteEthPHYGMIIRX(Module):
 # CRG is the only Xilinx specific module.
 # TODO: use generic code or add support for others vendors
 class LiteEthPHYGMIICRG(Module, AutoCSR):
-	def __init__(self, clock_pads, pads):
+	def __init__(self, clock_pads, pads, with_hw_init_reset):
 		self._reset = CSRStorage()
 		###
 		self.clock_domains.cd_eth_rx = ClockDomain()
@@ -49,7 +49,17 @@ class LiteEthPHYGMIICRG(Module, AutoCSR):
 		]
 		self.comb += self.cd_eth_tx.clk.eq(self.cd_eth_rx.clk)
 
-		reset = self._reset.storage
+		if with_hw_init_reset:
+			reset = Signal()
+			counter_done = Signal()
+			self.submodules.counter = counter = Counter(max=512)
+			self.comb += [
+				counter_done.eq(counter.value == 256),
+				counter.ce.eq(~counter_done),
+				reset.eq(~counter_done | self._reset.storage)
+			]
+		else:
+			reset = self._reset.storage
 		self.comb += pads.rst_n.eq(~reset)
 		self.specials += [
 			AsyncResetSynchronizer(self.cd_eth_tx, reset),
@@ -57,9 +67,9 @@ class LiteEthPHYGMIICRG(Module, AutoCSR):
 		]
 
 class LiteEthPHYGMII(Module, AutoCSR):
-	def __init__(self, clock_pads, pads):
+	def __init__(self, clock_pads, pads, with_hw_init_reset=True):
 		self.dw = 8
-		self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads)
+		self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset)
 		self.submodules.tx = RenameClockDomains(LiteEthPHYGMIITX(pads), "eth_tx")
 		self.submodules.rx = RenameClockDomains(LiteEthPHYGMIIRX(pads), "eth_rx")
 		self.sink, self.source = self.tx.sink, self.rx.source
diff --git a/liteeth/phy/mii.py b/liteeth/phy/mii.py
index fcf282d2..1dfda43a 100644
--- a/liteeth/phy/mii.py
+++ b/liteeth/phy/mii.py
@@ -90,7 +90,7 @@ class LiteEthPHYMIIRX(Module):
 		)
 
 class LiteEthPHYMIICRG(Module, AutoCSR):
-	def __init__(self, clock_pads, pads):
+	def __init__(self, clock_pads, pads, with_hw_init_reset):
 		self._reset = CSRStorage()
 		###
 		self.sync.base50 += clock_pads.phy.eq(~clock_pads.phy)
@@ -100,7 +100,17 @@ class LiteEthPHYMIICRG(Module, AutoCSR):
 		self.comb += self.cd_eth_rx.clk.eq(clock_pads.rx)
 		self.comb += self.cd_eth_tx.clk.eq(clock_pads.tx)
 
-		reset = self._reset.storage
+		if with_hw_init_reset:
+			reset = Signal()
+			counter_done = Signal()
+			self.submodules.counter = counter = Counter(max=512)
+			self.comb += [
+				counter_done.eq(counter.value == 256),
+				counter.ce.eq(~counter_done),
+				reset.eq(~counter_done | self._reset.storage)
+			]
+		else:
+			reset = self._reset.storage
 		self.comb += pads.rst_n.eq(~reset)
 		self.specials += [
 			AsyncResetSynchronizer(self.cd_eth_tx, reset),
@@ -108,9 +118,9 @@ class LiteEthPHYMIICRG(Module, AutoCSR):
 		]
 
 class LiteEthPHYMII(Module, AutoCSR):
-	def __init__(self, clock_pads, pads):
+	def __init__(self, clock_pads, pads, with_hw_init_reset=True):
 		self.dw = 8
-		self.submodules.crg = LiteEthPHYMIICRG(clock_pads, pads)
+		self.submodules.crg = LiteEthPHYMIICRG(clock_pads, pads, with_hw_init_reset)
 		self.submodules.tx = RenameClockDomains(LiteEthPHYMIITX(pads), "eth_tx")
 		self.submodules.rx = RenameClockDomains(LiteEthPHYMIIRX(pads), "eth_rx")
 		self.sink, self.source = self.tx.sink, self.rx.source