From: lkcl Date: Wed, 30 Dec 2020 17:13:30 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~702 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=929776e68744e55a4f7412fe8fd42837ef62876a;p=libreriscv.git --- diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn index 5dec88c8f..fc022fe90 100644 --- a/openpower/sv/overview.mdwn +++ b/openpower/sv/overview.mdwn @@ -76,7 +76,7 @@ basis further refinements can be added which build up towards an extremely powerful Vector augmentation system, with very little in the way of additional opcodes required: simply external "context". -x86 was originally only 70 instructions: prior to AVX512 1,400 additional ibsteuctions have been added, almost all of them related to SIMD. +x86 was originally only 80 instructions: prior to AVX512 over 1,300 additional instructions have been added, almost all of them SIMD. RISC-V RVV as of version 0.9 is over 188 instructions (more than the rest of RV64G combined: 80 for RV64G and 27 for C). Over 95% of that functionality is added to