From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 5 Jul 2013 17:33:42 +0000 (+0200)
Subject: Fixed vivado related xsthammer bugs
X-Git-Tag: yosys-0.2.0~547
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=92a5961fd3b1c880605b114edfbbafbefb20b377;p=yosys.git

Fixed vivado related xsthammer bugs
---

diff --git a/tests/xsthammer/report.sh b/tests/xsthammer/report.sh
index 868239078..d6ddd8628 100644
--- a/tests/xsthammer/report.sh
+++ b/tests/xsthammer/report.sh
@@ -32,6 +32,11 @@ cat ../../xl_cells.v ../../cy_cells.v > cells.v
 echo -n > fail_patterns.txt
 for p in syn_vivado syn_quartus syn_xst syn_yosys rtl; do
 for q in syn_vivado syn_quartus syn_xst syn_yosys rtl; do
+	if test -f result.${q}.${p}.txt; then
+		cp result.${q}.${p}.txt result.${p}.${q}.txt
+		continue
+	fi
+
 	{
 		echo "read_verilog -DGLBL $p.v"
 		echo "rename $job ${job}_1"
diff --git a/tests/xsthammer/run-vivado.sh b/tests/xsthammer/run-vivado.sh
index e8f574858..26a287d12 100644
--- a/tests/xsthammer/run-vivado.sh
+++ b/tests/xsthammer/run-vivado.sh
@@ -12,10 +12,11 @@ set -e
 mkdir -p vivado vivado_temp/$job
 cd vivado_temp/$job
 
+sed 's/^module/(* use_dsp48="no" *) module/;' < ../../rtl/$job.v > rtl.v
 cat > $job.tcl <<- EOT
-	read_verilog ../../rtl/$job.v
+	read_verilog rtl.v
 	synth_design -part xc7k70t -top $job
-	write_verilog ../../vivado/$job.v
+	write_verilog -force ../../vivado/$job.v
 EOT
 
 /opt/Xilinx/Vivado/2013.2/bin/vivado -mode batch -source $job.tcl
diff --git a/tests/xsthammer/xl_cells.v b/tests/xsthammer/xl_cells.v
index 3c1e77d2e..cfb2102fd 100644
--- a/tests/xsthammer/xl_cells.v
+++ b/tests/xsthammer/xl_cells.v
@@ -88,6 +88,12 @@ output O;
 assign O = S ? I1 : I0;
 endmodule
 
+module MUXF8(O, I0, I1, S);
+input I0, I1, S;
+output O;
+assign O = S ? I1 : I0;
+endmodule
+
 module VCC(P);
 output P;
 assign P = 1;