From: Sebastien Bourdeauducq Date: Sat, 9 Feb 2013 16:04:53 +0000 (+0100) Subject: sim: default runner to Icarus Verilog X-Git-Tag: 24jan2021_ls180~2099^2~700^2 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=92b67df41c49bffa4a65fa990b60ee13c29ad8f7;p=litex.git sim: default runner to Icarus Verilog --- diff --git a/doc/simulation.rst b/doc/simulation.rst index ce0a6d91..12827d16 100644 --- a/doc/simulation.rst +++ b/doc/simulation.rst @@ -36,8 +36,8 @@ Creating a simulator object The constructor of the ``Simulator`` object takes the following parameters: #. The fragment to simulate. The fragment can (and generally does) contain both synthesizable code and a non-synthesizable list of simulation functions. -#. A simulator runner object (see :ref:`simrunner`). #. A top-level object (see :ref:`toplevel`). With the default value of ``None``, the simulator creates a default top-level object itself. +#. A simulator runner object (see :ref:`simrunner`). With the default value of ``None``, Icarus Verilog is used with the default parameters. #. The name of the UNIX domain socket used to communicate with the external simulator through the VPI plug-in (default: "simsocket"). #. Additional keyword arguments (if any) are passed to the Verilog conversion function. diff --git a/examples/dataflow/dma.py b/examples/dataflow/dma.py index 98a3a2e1..322a6195 100644 --- a/examples/dataflow/dma.py +++ b/examples/dataflow/dma.py @@ -6,7 +6,6 @@ from migen.actorlib import dma_wishbone, dma_asmi from migen.actorlib.sim import * from migen.bus import wishbone, asmibus from migen.sim.generic import Simulator -from migen.sim.icarus import Runner class MyModel: def read(self, address): @@ -51,7 +50,7 @@ def wishbone_sim(efragment, master, end_simulation): + tap.get_fragment() \ + interconnect.get_fragment() \ + Fragment(sim=[_end_simulation]) - sim = Simulator(fragment, Runner()) + sim = Simulator(fragment) sim.run() def asmi_sim(efragment, hub, end_simulation): @@ -65,7 +64,7 @@ def asmi_sim(efragment, hub, end_simulation): + peripheral.get_fragment() \ + tap.get_fragment() \ + Fragment(sim=[_end_simulation]) - sim = Simulator(fragment, Runner()) + sim = Simulator(fragment) sim.run() def test_wb_reader(): diff --git a/examples/dataflow/misc.py b/examples/dataflow/misc.py index c8c0b734..14a6aa78 100644 --- a/examples/dataflow/misc.py +++ b/examples/dataflow/misc.py @@ -3,7 +3,6 @@ from migen.flow.transactions import * from migen.actorlib import misc from migen.actorlib.sim import * from migen.sim.generic import Simulator -from migen.sim.icarus import Runner def source_gen(): for i in range(10): @@ -26,7 +25,7 @@ def main(): g.add_connection(loop, sink) comp = CompositeActor(g) fragment = comp.get_fragment() - sim = Simulator(fragment, Runner()) + sim = Simulator(fragment) sim.run(500) main() diff --git a/examples/dataflow/structuring.py b/examples/dataflow/structuring.py index 9551e375..4d269611 100644 --- a/examples/dataflow/structuring.py +++ b/examples/dataflow/structuring.py @@ -8,7 +8,6 @@ from migen.flow.transactions import * from migen.actorlib import structuring from migen.actorlib.sim import * from migen.sim.generic import Simulator -from migen.sim.icarus import Runner from migen.flow import perftools pack_factor = 5 @@ -47,7 +46,7 @@ def main(): reporter = perftools.DFGReporter(g) fragment = comp.get_fragment() + reporter.get_fragment() - sim = Simulator(fragment, Runner()) + sim = Simulator(fragment) sim.run(1000) g_layout = nx.spectral_layout(g) diff --git a/examples/pytholite/basic.py b/examples/pytholite/basic.py index d00b1ddc..97e20a1d 100644 --- a/examples/pytholite/basic.py +++ b/examples/pytholite/basic.py @@ -3,7 +3,6 @@ from migen.flow.transactions import * from migen.actorlib.sim import * from migen.pytholite.compiler import make_pytholite from migen.sim.generic import Simulator -from migen.sim.icarus import Runner from migen.fhdl import verilog layout = [("r", 32)] @@ -19,7 +18,7 @@ def run_sim(ng): c = CompositeActor(g) fragment = c.get_fragment() - sim = Simulator(fragment, Runner()) + sim = Simulator(fragment) sim.run(30) del sim diff --git a/examples/pytholite/uio.py b/examples/pytholite/uio.py index 0798210b..42e66463 100644 --- a/examples/pytholite/uio.py +++ b/examples/pytholite/uio.py @@ -7,7 +7,6 @@ from migen.uio.ioo import UnifiedIOSimulation from migen.pytholite.transel import Register from migen.pytholite.compiler import make_pytholite from migen.sim.generic import Simulator -from migen.sim.icarus import Runner from migen.fhdl import verilog layout = [("r", 32)] @@ -40,7 +39,7 @@ def run_sim(ng): c = CompositeActor(g) fragment = slave.get_fragment() + intercon.get_fragment() + c.get_fragment() - sim = Simulator(fragment, Runner()) + sim = Simulator(fragment) sim.run(50) del sim diff --git a/examples/sim/abstract_transactions.py b/examples/sim/abstract_transactions.py index a27e90d1..bb69169d 100644 --- a/examples/sim/abstract_transactions.py +++ b/examples/sim/abstract_transactions.py @@ -8,7 +8,6 @@ from migen.fhdl import autofragment from migen.bus.transactions import * from migen.bus import wishbone, asmibus from migen.sim.generic import Simulator -from migen.sim.icarus import Runner # Our bus master. # Python generators let us program bus transactions in an elegant sequential style. @@ -67,7 +66,7 @@ def test_wishbone(): def end_simulation(s): s.interrupt = master.done fragment = autofragment.from_local() + Fragment(sim=[end_simulation]) - sim = Simulator(fragment, Runner()) + sim = Simulator(fragment) sim.run() def test_asmi(): @@ -85,7 +84,7 @@ def test_asmi(): def end_simulation(s): s.interrupt = master.done fragment = autofragment.from_local() + Fragment(sim=[end_simulation]) - sim = Simulator(fragment, Runner()) + sim = Simulator(fragment) sim.run() test_wishbone() diff --git a/examples/sim/basic1.py b/examples/sim/basic1.py index ac3f6fae..8cf4b4c2 100644 --- a/examples/sim/basic1.py +++ b/examples/sim/basic1.py @@ -3,7 +3,6 @@ from migen.fhdl.structure import * from migen.sim.generic import Simulator -from migen.sim.icarus import Runner # Our simple counter, which increments at every cycle # and prints its current value in simulation. @@ -31,9 +30,8 @@ class Counter: def main(): dut = Counter() - # Use the Icarus Verilog runner. - # We do not specify a top-level object, and use the default. - sim = Simulator(dut.get_fragment(), Runner()) + # We do not specify a top-level nor runner object, and use the defaults. + sim = Simulator(dut.get_fragment()) # Since we do not use sim.interrupt, limit the simulation # to some number of cycles. sim.run(20) diff --git a/examples/sim/basic2.py b/examples/sim/basic2.py index e0227f59..78fd2eeb 100644 --- a/examples/sim/basic2.py +++ b/examples/sim/basic2.py @@ -3,7 +3,6 @@ from migen.fhdl.structure import * from migen.sim.generic import Simulator, TopLevel -from migen.sim.icarus import Runner # A slightly improved counter. # Has a clock enable (CE) signal, counts on more bits @@ -46,7 +45,7 @@ def main(): dut = Counter() # Instantiating the generic top-level ourselves lets us # specify a VCD output file. - sim = Simulator(dut.get_fragment(), Runner(), TopLevel("my.vcd")) + sim = Simulator(dut.get_fragment(), TopLevel("my.vcd")) sim.run(20) main() diff --git a/examples/sim/dataflow.py b/examples/sim/dataflow.py index 172d2b9b..8e2628c8 100644 --- a/examples/sim/dataflow.py +++ b/examples/sim/dataflow.py @@ -4,7 +4,6 @@ from migen.flow.transactions import * from migen.flow.network import * from migen.actorlib.sim import * from migen.sim.generic import Simulator -from migen.sim.icarus import Runner def source_gen(): for i in range(10): @@ -26,7 +25,7 @@ def main(): def end_simulation(s): s.interrupt = source.token_exchanger.done fragment = comp.get_fragment() + Fragment(sim=[end_simulation]) - sim = Simulator(fragment, Runner()) + sim = Simulator(fragment) sim.run() main() diff --git a/examples/sim/fir.py b/examples/sim/fir.py index 218376bc..a2369503 100644 --- a/examples/sim/fir.py +++ b/examples/sim/fir.py @@ -10,7 +10,6 @@ from migen.fhdl import verilog from migen.corelogic.misc import optree from migen.fhdl import autofragment from migen.sim.generic import Simulator, PureSimulable -from migen.sim.icarus import Runner # A synthesizable FIR filter. class FIR: @@ -63,7 +62,7 @@ def main(): for frequency in [0.05, 0.07, 0.1, 0.15, 0.2]: tb = TB(fir, frequency) fragment = autofragment.from_local() - sim = Simulator(fragment, Runner()) + sim = Simulator(fragment) sim.run(100) del sim in_signals += tb.inputs diff --git a/examples/sim/memory.py b/examples/sim/memory.py index 1b1e67c7..7d66f234 100644 --- a/examples/sim/memory.py +++ b/examples/sim/memory.py @@ -3,7 +3,6 @@ from migen.fhdl.structure import * from migen.sim.generic import Simulator -from migen.sim.icarus import Runner class Mem: def __init__(self): @@ -29,7 +28,7 @@ class Mem: def main(): dut = Mem() - sim = Simulator(dut.get_fragment(), Runner()) + sim = Simulator(dut.get_fragment()) # No need for a cycle limit here, we use sim.interrupt instead. sim.run() diff --git a/migen/sim/generic.py b/migen/sim/generic.py index 2d69a8fe..cc72769f 100644 --- a/migen/sim/generic.py +++ b/migen/sim/generic.py @@ -4,6 +4,7 @@ from migen.fhdl.structure import * from migen.fhdl import verilog from migen.sim.ipc import * +from migen.sim import icarus class TopLevel: def __init__(self, vcd_name=None, vcd_level=1, @@ -73,13 +74,15 @@ end return r class Simulator: - def __init__(self, fragment, sim_runner, top_level=None, sockaddr="simsocket", **vopts): - self.fragment = fragment + def __init__(self, fragment, top_level=None, sim_runner=None, sockaddr="simsocket", **vopts): if top_level is None: - self.top_level = TopLevel() - else: - self.top_level = top_level + top_level = TopLevel() + if sim_runner is None: + sim_runner = icarus.Runner() + self.fragment = fragment + self.top_level = top_level self.ipc = Initiator(sockaddr) + self.sim_runner = sim_runner c_top = self.top_level.get(sockaddr)