From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 21 Jan 2020 00:42:17 +0000 (-0800)
Subject: +/cmp2lcu.v to work efficiently for fully/partially constant inputs
X-Git-Tag: working-ls180~695^2~7
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=92d70cafec026fb25bf45b020c138e5244bb8cdc;p=yosys.git

+/cmp2lcu.v to work efficiently for fully/partially constant inputs
---

diff --git a/tests/techmap/cmp2lcu.ys b/tests/techmap/cmp2lcu.ys
index 620996549..7c8a63692 100644
--- a/tests/techmap/cmp2lcu.ys
+++ b/tests/techmap/cmp2lcu.ys
@@ -10,15 +10,43 @@ assign leu = a <= b;
 assign les = $signed(a) <= $signed(b);
 endmodule
 EOT
-proc
 
 equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=6
 design -load postopt
-select -assert-count 8 t:$lcu
+select -assert-count 8 t:$lcu r:WIDTH=5 %i
 select -assert-none t:$gt t:$ge t:$lt t:$le
 
 design -load preopt
 equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=4
 design -load postopt
-select -assert-count 8 t:$lcu
+select -assert-count 8 t:$lcu r:WIDTH=7 %i
+select -assert-none t:$gt t:$ge t:$lt t:$le
+
+
+design -reset
+read_verilog <<EOT
+module top(input [8:0] a, b, output gtu, gts, ltu, lts, geu, ges, leu, les);
+wire [13:0] c = {a[8:6], 3'b101, a[5:4], 2'b11, a[3:0]};
+wire [13:0] d = {b[8], 3'b101, b[7:4], 2'b01, b[3:0]};
+assign gtu = c > d;
+assign gts = $signed(c) > $signed(d);
+assign ltu = c < d;
+assign lts = $signed(c) < $signed(d);
+assign geu = c >= d;
+assign ges = $signed(c) >= $signed(d);
+assign leu = c <= d;
+assign les = $signed(c) <= $signed(d);
+endmodule
+EOT
+design -save gold
+
+equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=5
+design -load postopt
+select -assert-count 8 t:$lcu r:WIDTH=2 %i
+select -assert-none t:$gt t:$ge t:$lt t:$le
+
+design -load preopt
+equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=3
+design -load postopt
+select -assert-count 8 t:$lcu r:WIDTH=4 %i
 select -assert-none t:$gt t:$ge t:$lt t:$le