From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 15 Sep 2020 15:22:01 +0000 (+0100)
Subject: add OP_DCBZ to mmu fsm, needs RA to be added to MMU pipe_data
X-Git-Tag: semi_working_ecp5~27
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=92e4fcd9e6240854b5195911533ed58e096b549e;p=soc.git

add OP_DCBZ to mmu fsm, needs RA to be added to MMU pipe_data
---

diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index 004e2f35..82f948d2 100644
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -47,6 +47,7 @@ class FSMMMUStage(ControlBase):
         m.d.comb += mmu.d_in.eq(dcache.m_out)
 
         data_i, data_o = self.p.data_i, self.n.data_o
+        a_i, b_i = data_i.ra, data_i.rb
         op = data_i.ctx.op
 
         # busy/done signals
@@ -77,11 +78,18 @@ class FSMMMUStage(ControlBase):
                     # pass it over to the MMU instead
                     with m.Else():
                         # kick the MMU and wait for it to complete
-                        comb += mmu.valid.eq(1)   # start
-                        comb += mmu.mtspr.eq(1)   # mtspr mode
-                        comb += mmu.sprn.eq(spr)  # which SPR
-                        comb += mmu.rs.eq(a_i)    # incoming operand (RS)
-                        comb += done.eq(mmu.done) # zzzz
+                        comb += mmu.m_in.valid.eq(1)   # start
+                        comb += mmu.m_in.mtspr.eq(1)   # mtspr mode
+                        comb += mmu.m_in.sprn.eq(spr)  # which SPR
+                        comb += mmu.m_in.rs.eq(a_i)    # incoming operand (RS)
+                        comb += done.eq(mmu.m_out.done) # zzzz
+
+                with m.Case(OP_DCBZ):
+                    # activate dcbz mode (spec: v3.0B p850)
+                    comb += dcache.d_in.valid.eq(1)        # start
+                    comb += dcache.d_in.dcbz.eq(1)         # dcbz mode
+                    comb += dcache.d_in.addr.eq(a_i + b_i) # addr is (RA|0) + RB
+                    comb += done.eq(dcache.d_out.done)      # zzzz
 
             with m.If(self.n.ready_i & self.n.valid_o):
                 m.d.sync += busy.eq(0)
diff --git a/src/soc/fu/mmu/pipe_data.py b/src/soc/fu/mmu/pipe_data.py
index 4116a781..2c2a45ca 100644
--- a/src/soc/fu/mmu/pipe_data.py
+++ b/src/soc/fu/mmu/pipe_data.py
@@ -3,7 +3,7 @@
 Covers MFMMU and MTMMU for MMU MMUs (dsisr, dar), and DCBZ and TLBIE.
 
 Interestingly none of the MMU instructions use RA, they all use RB.
-go with it...
+except dcbz which uses (RA|0)
 
 Links:
 * https://bugs.libre-soc.org/show_bug.cgi?id=491
@@ -16,13 +16,15 @@ from soc.fu.alu.pipe_data import CommonPipeSpec
 
 
 class MMUInputData(IntegerData):
-    regspec = [('INT', 'rb', '0:63'),        # RB
+    regspec = [('INT', 'ra', '0:63'),        # RA
+               ('INT', 'rb', '0:63'),        # RB
                ('SPR', 'spr1', '0:63'),      # MMU (slow)
                ('FAST', 'fast1', '0:63'),    # MMU (fast: LR, CTR etc)
                ]   
     def __init__(self, pspec):
         super().__init__(pspec, False)
         # convenience
+        self.a = self.ra
         self.b = self.rb