From: richard Date: Fri, 1 Oct 2010 20:10:02 +0000 (-0400) Subject: evergreen : fix z format setting, enable stencil. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=92eb07a281d3b8748b5570d502c98aca654823de;p=mesa.git evergreen : fix z format setting, enable stencil. --- diff --git a/src/mesa/drivers/dri/r600/evergreen_chip.c b/src/mesa/drivers/dri/r600/evergreen_chip.c index 16627418232..b591d5fa27c 100644 --- a/src/mesa/drivers/dri/r600/evergreen_chip.c +++ b/src/mesa/drivers/dri/r600/evergreen_chip.c @@ -876,13 +876,13 @@ static void evergreenSetDepthTarget(context_t *context) if(4 == rrb->cpp) { - SETfield(evergreen->DB_Z_INFO.u32All, DEPTH_8_24, + SETfield(evergreen->DB_Z_INFO.u32All, EG_Z_24, EG_DB_Z_INFO__FORMAT_shift, EG_DB_Z_INFO__FORMAT_mask); } else { - SETfield(evergreen->DB_Z_INFO.u32All, DEPTH_16, + SETfield(evergreen->DB_Z_INFO.u32All, EG_Z_16, EG_DB_Z_INFO__FORMAT_shift, EG_DB_Z_INFO__FORMAT_mask); } @@ -896,6 +896,7 @@ static void evergreenSendDB(GLcontext *ctx, struct radeon_state_atom *atom) context_t *context = EVERGREEN_CONTEXT(ctx); EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context); struct radeon_renderbuffer *rrb; + unsigned int zheight, zpitch, offtostencil; BATCH_LOCALS(&context->radeon); radeon_print(RADEON_STATE, RADEON_VERBOSE, "%s\n", __func__); @@ -949,17 +950,28 @@ static void evergreenSendDB(GLcontext *ctx, struct radeon_state_atom *atom) END_BATCH(); rrb = radeon_get_depthbuffer(&context->radeon); + + if (context->radeon.radeonScreen->driScreen->dri2.enabled) + { + zheight = rrb->base.Height; + } + else + { + zheight = context->radeon.radeonScreen->driScreen->fbHeight; + } + zpitch = rrb->pitch; + if( (rrb != NULL) && (rrb->bo != NULL) ) { /* make the hw happy */ BEGIN_BATCH_NO_AUTOSTATE(3 + 2); - EVERGREEN_OUT_BATCH_REGVAL(EG_DB_HTILE_DATA_BASE, evergreen->DB_HTILE_DATA_BASE.u32All); - R600_OUT_BATCH_RELOC(evergreen->DB_HTILE_DATA_BASE.u32All, + EVERGREEN_OUT_BATCH_REGVAL(EG_DB_HTILE_DATA_BASE, evergreen->DB_HTILE_DATA_BASE.u32All); + R600_OUT_BATCH_RELOC(evergreen->DB_HTILE_DATA_BASE.u32All, rrb->bo, evergreen->DB_HTILE_DATA_BASE.u32All, 0, RADEON_GEM_DOMAIN_VRAM, 0); - END_BATCH(); + END_BATCH(); //5 BEGIN_BATCH_NO_AUTOSTATE(3 + 2); @@ -993,27 +1005,37 @@ static void evergreenSendDB(GLcontext *ctx, struct radeon_state_atom *atom) END_BATCH(); } } -/* + if (ctx->DrawBuffer) { rrb = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL); if((rrb != NULL) && (rrb->bo != NULL)) - { + { //5 BEGIN_BATCH_NO_AUTOSTATE(3 + 2); - EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_INFO, evergreen->DB_Z_INFO.u32All); + EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_INFO, evergreen->DB_STENCIL_INFO.u32All); R600_OUT_BATCH_RELOC(evergreen->DB_STENCIL_INFO.u32All, rrb->bo, evergreen->DB_STENCIL_INFO.u32All, 0, RADEON_GEM_DOMAIN_VRAM, 0); END_BATCH(); + + //4 + BEGIN_BATCH_NO_AUTOSTATE(4); + R600_OUT_BATCH_REGSEQ(DB_STENCILREFMASK, 2); + R600_OUT_BATCH(evergreen->DB_STENCILREFMASK.u32All); + R600_OUT_BATCH(evergreen->DB_STENCILREFMASK_BF.u32All); + END_BATCH(); + //------------------------ //10 if((evergreen->DB_DEPTH_CONTROL.u32All & STENCIL_ENABLE_bit) > 0) { - BEGIN_BATCH_NO_AUTOSTATE(3 + 2); - EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_READ_BASE, evergreen->DB_STENCIL_READ_BASE.u32All); + offtostencil = ((zheight * zpitch + 255) >> 8) & 0xffffffff; + + BEGIN_BATCH_NO_AUTOSTATE(3 + 2); + EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_READ_BASE, offtostencil); R600_OUT_BATCH_RELOC(evergreen->DB_STENCIL_READ_BASE.u32All, rrb->bo, evergreen->DB_STENCIL_READ_BASE.u32All, @@ -1021,7 +1043,7 @@ static void evergreenSendDB(GLcontext *ctx, struct radeon_state_atom *atom) END_BATCH(); BEGIN_BATCH_NO_AUTOSTATE(3 + 2); - EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_WRITE_BASE, evergreen->DB_STENCIL_WRITE_BASE.u32All); + EVERGREEN_OUT_BATCH_REGVAL(EG_DB_STENCIL_WRITE_BASE, offtostencil); R600_OUT_BATCH_RELOC(evergreen->DB_STENCIL_WRITE_BASE.u32All, rrb->bo, evergreen->DB_STENCIL_WRITE_BASE.u32All, @@ -1030,7 +1052,7 @@ static void evergreenSendDB(GLcontext *ctx, struct radeon_state_atom *atom) } } } -*/ + COMMIT_BATCH(); } @@ -1508,7 +1530,7 @@ void evergreenInitAtoms(context_t *context) EVERGREEN_ALLOC_STATE(spi, always, 59, evergreenSendSPI); EVERGREEN_ALLOC_STATE(sx, always, 9, evergreenSendSX); EVERGREEN_ALLOC_STATE(tx, evergreen_tx, (R700_TEXTURE_NUMBERUNITS * (21+5) + 6), evergreenSendTexState); /* 21 for resource, 5 for sampler */ - EVERGREEN_ALLOC_STATE(db, always, 65, evergreenSendDB); + EVERGREEN_ALLOC_STATE(db, always, 69, evergreenSendDB); EVERGREEN_ALLOC_STATE(cb, always, 37, evergreenSendCB); EVERGREEN_ALLOC_STATE(vgt, always, 29, evergreenSendVGT); diff --git a/src/mesa/drivers/dri/r600/evergreen_state.c b/src/mesa/drivers/dri/r600/evergreen_state.c index 931478caa5a..69c5ab656ea 100644 --- a/src/mesa/drivers/dri/r600/evergreen_state.c +++ b/src/mesa/drivers/dri/r600/evergreen_state.c @@ -703,24 +703,25 @@ static void evergreenSetDepthState(GLcontext * ctx) //same static void evergreenSetStencilState(GLcontext * ctx, GLboolean state) //same { - context_t *context = EVERGREEN_CONTEXT(ctx); - EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context); - GLboolean hw_stencil = GL_FALSE; + context_t *context = EVERGREEN_CONTEXT(ctx); + EVERGREEN_CHIP_CONTEXT *evergreen = GET_EVERGREEN_CHIP(context); + GLboolean hw_stencil = GL_FALSE; - if (ctx->DrawBuffer) { - struct radeon_renderbuffer *rrbStencil - = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL); - hw_stencil = (rrbStencil && rrbStencil->bo); - } + if (ctx->DrawBuffer) { + struct radeon_renderbuffer *rrbStencil + = radeon_get_renderbuffer(ctx->DrawBuffer, BUFFER_STENCIL); + hw_stencil = (rrbStencil && rrbStencil->bo); + } - if (hw_stencil) { - EVERGREEN_STATECHANGE(context, db); - if (state) { - SETbit(evergreen->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit); - SETbit(evergreen->DB_DEPTH_CONTROL.u32All, BACKFACE_ENABLE_bit); - } else - CLEARbit(evergreen->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit); - } + if (hw_stencil) { + EVERGREEN_STATECHANGE(context, db); + if (state) { + SETbit(evergreen->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit); + SETbit(evergreen->DB_DEPTH_CONTROL.u32All, BACKFACE_ENABLE_bit); + SETbit(evergreen->DB_STENCIL_INFO.u32All, EG_DB_STENCIL_INFO__FORMAT_bit); + } else + CLEARbit(evergreen->DB_DEPTH_CONTROL.u32All, STENCIL_ENABLE_bit); + } } static void evergreenUpdateCulling(GLcontext * ctx) //same @@ -1699,7 +1700,7 @@ void evergreenInitState(GLcontext * ctx) //diff evergreen->DB_STENCIL_INFO.u32All = 0; CLEARbit(evergreen->DB_STENCIL_INFO.u32All, EG_DB_STENCIL_INFO__FORMAT_bit); - SETfield(evergreen->DB_STENCIL_INFO.u32All, EG_ADDR_SURF_TILE_SPLIT_256B, + SETfield(evergreen->DB_STENCIL_INFO.u32All, 0, EG_DB_STENCIL_INFO__TILE_SPLIT_shift, EG_DB_STENCIL_INFO__TILE_SPLIT_mask); evergreen->DB_RENDER_CONTROL.u32All = 0; @@ -1709,6 +1710,15 @@ void evergreenInitState(GLcontext * ctx) //diff SETfield(evergreen->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask); SETfield(evergreen->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask); + /* stencil */ + evergreenEnable(ctx, GL_STENCIL_TEST, ctx->Stencil._Enabled); + evergreenStencilMaskSeparate(ctx, 0, ctx->Stencil.WriteMask[0]); + evergreenStencilFuncSeparate(ctx, 0, ctx->Stencil.Function[0], + ctx->Stencil.Ref[0], ctx->Stencil.ValueMask[0]); + evergreenStencilOpSeparate(ctx, 0, ctx->Stencil.FailFunc[0], + ctx->Stencil.ZFailFunc[0], + ctx->Stencil.ZPassFunc[0]); + // Disable ROP3 modes by setting src to dst copy: SETfield(evergreen->CB_COLOR_CONTROL.u32All, 0xCC, EG_CB_COLOR_CONTROL__ROP3_shift,