From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 30 Sep 2022 08:14:26 +0000 (+0100)
Subject: whitespace
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=92f0d24fa53c23a31ec51d4e386ce5f6a288c5bc;hp=38c05ffbdd2e98659842bb49aad5f28add0fc8ef;p=openpower-isa.git

whitespace
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 71cd92c8..40fcdd44 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -282,9 +282,8 @@ class CRFields:
             _cr = FieldSelectableInt(self.cr, bits)
             self.crl.append(_cr)
 
-# decode SVP64 predicate integer to reg number and invert
-
 
+# decode SVP64 predicate integer to reg number and invert
 def get_predint(gpr, mask):
     r3 = gpr(3)
     r10 = gpr(10)
@@ -307,9 +306,8 @@ def get_predint(gpr, mask):
     if mask == SVP64PredInt.R30_N.value:
         return ~r30.value
 
-# decode SVP64 predicate CR to reg number and invert status
-
 
+# decode SVP64 predicate CR to reg number and invert status
 def _get_predcr(mask):
     if mask == SVP64PredCR.LT.value:
         return 0, 1
@@ -328,10 +326,9 @@ def _get_predcr(mask):
     if mask == SVP64PredCR.NS.value:
         return 3, 0
 
+
 # read individual CR fields (0..VL-1), extract the required bit
 # and construct the mask
-
-
 def get_predcr(crl, mask, vl):
     idx, noninv = _get_predcr(mask)
     mask = 0