From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Tue, 13 Dec 2011 13:08:39 +0000 (+0100)
Subject: wishbone: decoder: fix slave cyc generation in registered mode
X-Git-Tag: 24jan2021_ls180~2099^2~1139
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=92f24b784ddf822e39743288d331199a9691257a;p=litex.git

wishbone: decoder: fix slave cyc generation in registered mode
---

diff --git a/migen/bus/wishbone.py b/migen/bus/wishbone.py
index bca7fce4..b464adea 100644
--- a/migen/bus/wishbone.py
+++ b/migen/bus/wishbone.py
@@ -113,7 +113,7 @@ class Decoder:
 		# combine cyc with slave selection signals
 		i = 0
 		for slave in self.slaves:
-			comb.append(f.Assign(slave[1].cyc_i, self.master.cyc_o & self._slave_sel_r[i]))
+			comb.append(f.Assign(slave[1].cyc_i, self.master.cyc_o & self._slave_sel[i]))
 			i += 1
 		
 		# generate master ack (resp. err) by ORing all slave acks (resp. errs)