From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 25 Mar 2022 14:53:14 +0000 (+0000)
Subject: up arty a7 frequency to 40 mhz
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=92fd6f9e65a1d2d19182cd6f03e06b3462bbb19f;p=ls2.git

up arty a7 frequency to 40 mhz
---

diff --git a/src/ls2.py b/src/ls2.py
index e458989..7d79c24 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -589,7 +589,7 @@ def build_platform(fpga, firmware):
     if fpga == 'arty_a7':
         clk_freq = 50e6
     if fpga == 'ulx3s':
-        clk_freq = 25.0e6
+        clk_freq = 40.0e6
 
     # select a firmware address
     fw_addr = None