From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 1 Sep 2022 15:42:14 +0000 (+0100)
Subject: begin rename of RC to FLAGS and add RC_OE/RC_ONLY
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9310953672edb4f7f77b65a3bef2af4b715d915b;p=openpower-isa.git

begin rename of RC to FLAGS and add RC_OE/RC_ONLY
---

diff --git a/src/openpower/decoder/power_decoder.py b/src/openpower/decoder/power_decoder.py
index 9da38df7..d4cafe90 100644
--- a/src/openpower/decoder/power_decoder.py
+++ b/src/openpower/decoder/power_decoder.py
@@ -94,7 +94,7 @@ from nmigen.cli import rtlil, verilog
 from openpower.decoder.power_enums import (Function, Form, MicrOp,
                                            In1Sel, In2Sel, In3Sel, OutSel,
                                            SVEXTRA, SVEtype, SVPtype, # Simple-V
-                                           RC, LdstLen, LDSTMode, CryIn,
+                                           FLAGS, LdstLen, LDSTMode, CryIn,
                                            single_bit_flags, CRInSel,
                                            CROutSel, get_signal_name,
                                            default_values, insns, asmidx,
@@ -140,7 +140,7 @@ power_op_types = {'function_unit': Function,
                   'sv_cr_out': SVEXTRA,
                   'ldst_len': LdstLen,
                   'upd': LDSTMode,
-                  'rc_sel': RC,
+                  'rc_sel': FLAGS,
                   'cry_in': CryIn
                   }
 
diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py
index 70258d78..5675c27e 100644
--- a/src/openpower/decoder/power_decoder2.py
+++ b/src/openpower/decoder/power_decoder2.py
@@ -31,7 +31,7 @@ from openpower.decoder.power_enums import (MicrOp, CryIn, Function,
                                            CRInSel, CROutSel,
                                            LdstLen, In1Sel, In2Sel, In3Sel,
                                            OutSel, SPRfull, SPRreduced,
-                                           RC, SVP64LDSTmode, LDSTMode,
+                                           FLAGS, SVP64LDSTmode, LDSTMode,
                                            SVEXTRA, SVEtype, SVPtype)
 from openpower.decoder.decode2execute1 import (Decode2ToExecute1Type, Data,
                                                Decode2ToOperand)
@@ -529,7 +529,7 @@ class DecodeRC(Elaboratable):
 
     def __init__(self, dec):
         self.dec = dec
-        self.sel_in = Signal(RC, reset_less=True)
+        self.sel_in = Signal(FLAGS, reset_less=True)
         self.insn_in = Signal(32, reset_less=True)
         self.rc_out = Data(1, "rc")
 
@@ -539,13 +539,13 @@ class DecodeRC(Elaboratable):
 
         # select Record bit out field
         with m.Switch(self.sel_in):
-            with m.Case(RC.RC):
+            with m.Case(FLAGS.RC_OE, FLAGS.RC_ONLY):
                 comb += self.rc_out.data.eq(self.dec.Rc)
                 comb += self.rc_out.ok.eq(1)
-            with m.Case(RC.ONE):
+            with m.Case(FLAGS.ONE):
                 comb += self.rc_out.data.eq(1)
                 comb += self.rc_out.ok.eq(1)
-            with m.Case(RC.NONE):
+            with m.Case(FLAGS.NONE):
                 comb += self.rc_out.data.eq(0)
                 comb += self.rc_out.ok.eq(1)
 
@@ -567,7 +567,7 @@ class DecodeOE(Elaboratable):
     def __init__(self, dec, op):
         self.dec = dec
         self.op = op
-        self.sel_in = Signal(RC, reset_less=True)
+        self.sel_in = Signal(FLAGS, reset_less=True)
         self.insn_in = Signal(32, reset_less=True)
         self.oe_out = Data(1, "oe")
 
@@ -605,7 +605,7 @@ class DecodeOE(Elaboratable):
             with m.Default():
                 # select OE bit out field
                 with m.Switch(self.sel_in):
-                    with m.Case(RC.RC):
+                    with m.Case(FLAGS.RC_OE):
                         comb += self.oe_out.data.eq(self.dec.OE)
                         comb += self.oe_out.ok.eq(1)