From: Ron Dreslinski <rdreslin@umich.edu>
Date: Mon, 17 Jan 2005 19:57:26 +0000 (-0500)
Subject: Changes neccesary to support full system coherence on the first level of caches with... 
X-Git-Tag: m5_1.0_tutorial~111
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=93146bc81a391fc298c2b49e2b3ecf969ae93b72;p=gem5.git

Changes neccesary to support full system coherence on the first level of caches with a event based bus
-Change how the blocking is implemented
-Update coherence policy state table to include sotware prefetches and DMA requests

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extra : convert_revision : 80f37dc1c7221b684888e859b534d008c578669c
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