From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 28 Aug 2019 17:51:39 +0000 (-0700)
Subject: Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor
X-Git-Tag: working-ls180~1092
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9314a0a42ec05e82d2d3d77aebddfb06271a4730;p=yosys.git

Add (* clkbuf_sink *) to SRLC16E, reorder ports to match vendor
---

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 973e17212..e12b77c02 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -380,9 +380,10 @@ endmodule
 
 module SRL16E (
   output Q,
+  input A0, A1, A2, A3, CE,
   (* clkbuf_sink *)
   input CLK,
-  input A0, A1, A2, A3, CE, D
+  input D
 );
   parameter [15:0] INIT = 16'h0000;
   parameter [0:0] IS_CLK_INVERTED = 1'b0;
@@ -401,7 +402,10 @@ endmodule
 module SRLC16E (
   output Q,
   output Q15,
-  input A0, A1, A2, A3, CE, CLK, D
+  input A0, A1, A2, A3, CE,
+  (* clkbuf_sink *)
+  input CLK,
+  input D
 );
   parameter [15:0] INIT = 16'h0000;
   parameter [0:0] IS_CLK_INVERTED = 1'b0;
@@ -422,9 +426,10 @@ module SRLC32E (
   output Q,
   output Q31,
   input [4:0] A,
+  input CE,
   (* clkbuf_sink *)
   input CLK,
-  input CE, D
+  input D
 );
   parameter [31:0] INIT = 32'h00000000;
   parameter [0:0] IS_CLK_INVERTED = 1'b0;