From: Mateusz Holenko <mholenko@antmicro.com>
Date: Thu, 25 Jul 2019 06:43:35 +0000 (+0200)
Subject: cpu/vexriscv: bump submodule
X-Git-Tag: 24jan2021_ls180~1078^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=932475a29b07e0f5c958b35bc0e30751bebc7ef0;p=litex.git

cpu/vexriscv: bump submodule
---

diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog
index 747a2e01..854f9bd2 160000
--- a/litex/soc/cores/cpu/vexriscv/verilog
+++ b/litex/soc/cores/cpu/vexriscv/verilog
@@ -1 +1 @@
-Subproject commit 747a2e012f43d13c3487acc3c758477aad277559
+Subproject commit 854f9bd2282c97251ce65e4117c5cf1630722004