From: lkcl <lkcl@web>
Date: Sat, 2 Apr 2022 10:43:51 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2937
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9327ff9a7f3db01998cf25b981979cb2d1099d3f;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index fb9aaf36d..3bf996d0b 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -190,7 +190,9 @@ Scalar v3.0B Branches. `bclr` for example will always update LR, whereas
 It is important to keep in mind that just like all SVP64 instructions,
 the `BI` field of the base v3.0B Branch Conditional instruction
 may be extended by SVP64 EXTRA augmentation, as well as be marked
-as either Scalar or Vector.
+as either Scalar or Vector. It is also crucially important to be reminded
+that SVP64 sequentially increments the CR *Field* numbers.
+CR *Fields* are treated as elrments, not bit-numbers of the CR *register*.
 
 The `BI` field of Branch Conditional operations is five bits, in scalar
 v3.0B this would select one bit of the 32 bit CR,