From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 6 Sep 2014 18:30:46 +0000 (+0200)
Subject: Various bug fixes (related to $macc model testing)
X-Git-Tag: yosys-0.4~153
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9329a768181d3765a08c3b264c8b0031b732c0d4;p=yosys.git

Various bug fixes (related to $macc model testing)
---

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 82a2c519e..bbdbbbfaf 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -973,7 +973,8 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 			for (int i = 0; i < wire->width; i++)
 				if (reg_bits.count(std::pair<RTLIL::Wire*,int>(wire, i)) == 0)
 					goto this_wire_aint_reg;
-			reg_wires.insert(wire->name);
+			if (wire->width)
+				reg_wires.insert(wire->name);
 		this_wire_aint_reg:;
 		}
 	}
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
index edab51eb2..c69bd123b 100644
--- a/passes/tests/test_cell.cc
+++ b/passes/tests/test_cell.cc
@@ -262,7 +262,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, std::string uut_n
 			gold_ce.set(gold_wire, in_value);
 			gate_ce.set(gate_wire, in_value);
 
-			if (vlog_file.is_open()) {
+			if (vlog_file.is_open() && SIZE(in_value) > 0) {
 				vlog_file << stringf("      %s = 'b%s;\n", log_id(gold_wire), in_value.as_string().c_str());
 				if (!vlog_pattern_info.empty())
 					vlog_pattern_info += " ";
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index b1f871d9b..465efc0a7 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -768,7 +768,7 @@ module \$macc (A, B, Y);
 
 	localparam integer num_bits = CONFIG[3:0];
 	localparam integer num_ports = (CONFIG_WIDTH-4) / (2 + 2*num_bits);
-	localparam integer num_abits = $clog2(A_WIDTH);
+	localparam integer num_abits = $clog2(A_WIDTH) > 0 ? $clog2(A_WIDTH) : 1;
 
 	function [2*num_ports*num_abits-1:0] get_port_offsets;
 		input [CONFIG_WIDTH-1:0] cfg;
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index f0397858f..3fc6ccb8e 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -594,7 +594,7 @@ module \$macc (A, B, Y);
 
 	localparam integer num_bits = CONFIG[3:0];
 	localparam integer num_ports = (CONFIG_WIDTH-4) / (2 + 2*num_bits);
-	localparam integer num_abits = $clog2(A_WIDTH);
+	localparam integer num_abits = $clog2(A_WIDTH) > 0 ? $clog2(A_WIDTH) : 1;
 
 	function [2*num_ports*num_abits-1:0] get_port_offsets;
 		input [CONFIG_WIDTH-1:0] cfg;