From: Walter Lee <walt@tilera.com>
Date: Wed, 27 Mar 2013 06:17:18 +0000 (+0000)
Subject: tilegx.md (insn_v1mulu): Fix constraints on input operands.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9332b0d294bb48fa556aebc6c3eba1841f848b8a;p=gcc.git

tilegx.md (insn_v1mulu): Fix constraints on input operands.

	* config/tilegx/tilegx.md (insn_v1mulu): Fix constraints on
	input operands.
	(insn_v1mulus): Ditto.
	(insn_v2muls): Ditto.

From-SVN: r197138
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6925928280b..919d3d720ab 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2013-03-27  Walter Lee  <walt@tilera.com>
+
+	* config/tilegx/tilegx.md (insn_v1mulu): Fix constraints on
+	input operands.
+	(insn_v1mulus): Ditto.
+	(insn_v2muls): Ditto.
+
 2013-03-27  Walter Lee  <walt@tilera.com>
 
 	* config/tilegx/tilegx.h (ASM_OUTPUT_ADDR_VEC_ELT): Delete
diff --git a/gcc/config/tilegx/tilegx.md b/gcc/config/tilegx/tilegx.md
index 09bcc5ab015..9c6917059a1 100644
--- a/gcc/config/tilegx/tilegx.md
+++ b/gcc/config/tilegx/tilegx.md
@@ -4762,8 +4762,8 @@
 
 (define_expand "insn_v1mulu"
   [(match_operand:DI 0 "register_operand" "")
-   (match_operand:DI 1 "reg_or_0_operand" "")
-   (match_operand:DI 2 "reg_or_0_operand" "")]
+   (match_operand:DI 1 "register_operand" "")
+   (match_operand:DI 2 "register_operand" "")]
   ""
 {
   tilegx_expand_builtin_vector_binop (gen_vec_widen_umult_lo_v8qi, V4HImode,
@@ -4792,8 +4792,8 @@
 
 (define_expand "insn_v1mulus"
   [(match_operand:DI 0 "register_operand" "")
-   (match_operand:DI 1 "reg_or_0_operand" "")
-   (match_operand:DI 2 "reg_or_0_operand" "")]
+   (match_operand:DI 1 "register_operand" "")
+   (match_operand:DI 2 "register_operand" "")]
   ""
 {
   tilegx_expand_builtin_vector_binop (gen_vec_widen_usmult_lo_v8qi, V4HImode,
@@ -4820,8 +4820,8 @@
 
 (define_expand "insn_v2muls"
   [(match_operand:DI 0 "register_operand" "")
-   (match_operand:DI 1 "reg_or_0_operand" "")
-   (match_operand:DI 2 "reg_or_0_operand" "")]
+   (match_operand:DI 1 "register_operand" "")
+   (match_operand:DI 2 "register_operand" "")]
   ""
 {
   tilegx_expand_builtin_vector_binop (gen_vec_widen_smult_lo_v4qi, V2SImode,