From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 19 Jan 2018 15:20:40 +0000 (+0100)
Subject: Improve log messages in equiv_make
X-Git-Tag: yosys-0.8~230
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9337e4999dcd32530c15cb618cd106698680e431;p=yosys.git

Improve log messages in equiv_make

Signed-off-by: Clifford Wolf <clifford@clifford.at>
---

diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc
index 40ca42621..b20463777 100644
--- a/passes/equiv/equiv_make.cc
+++ b/passes/equiv/equiv_make.cc
@@ -260,11 +260,11 @@ struct EquivMakeWorker
 
 				for (int i = 0; i < wire->width; i++) {
 					if (undriven_bits.count(assign_map(SigBit(gold_wire, i)))) {
-						log("  Skipping signal bit %d: undriven on gold side.\n", i);
+						log("  Skipping signal bit %s [%d]: undriven on gold side.\n", id2cstr(gold_wire->name), i);
 						continue;
 					}
 					if (undriven_bits.count(assign_map(SigBit(gate_wire, i)))) {
-						log("  Skipping signal bit %d: undriven on gate side.\n", i);
+						log("  Skipping signal bit %s [%d]: undriven on gate side.\n", id2cstr(gate_wire->name), i);
 						continue;
 					}
 					equiv_mod->addEquiv(NEW_ID, SigSpec(gold_wire, i), SigSpec(gate_wire, i), SigSpec(wire, i));