From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 20 Feb 2014 22:44:28 +0000 (+0100)
Subject: Progress in presentation
X-Git-Tag: yosys-0.3.0~124
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9351e4d3caef1af7b7768d66b7f6edc12713d109;p=yosys.git

Progress in presentation
---

diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_test.v b/manual/PRESENTATION_ExAdv/macc_xilinx_test.v
index d08d939e9..d8fdf724c 100644
--- a/manual/PRESENTATION_ExAdv/macc_xilinx_test.v
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_test.v
@@ -1,6 +1,13 @@
-module test(a, b, c, d, e, f, y);
+module test1(a, b, c, d, e, f, y);
 input [19:0] a, b, c;
 input [15:0] d, e, f;
 output [41:0] y;
 assign y = a*b + c*d + e*f;
 endmodule
+
+module test2(a, b, c, d, e, f, y);
+input [19:0] a, b, c;
+input [15:0] d, e, f;
+output [41:0] y;
+assign y = a*b + (c*d + e*f);
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys b/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
index 8cbc80b5e..85c4a24f6 100644
--- a/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_test.ys
@@ -1,17 +1,40 @@
 read_verilog macc_xilinx_test.v
 read_verilog -lib -icells macc_xilinx_unwrap_map.v
-hierarchy -check -top test;;
+read_verilog -lib -icells macc_xilinx_xmap.v
+hierarchy -check ;;
 
-show -prefix macc_xilinx_test_a -format pdf -notitle
+show -prefix macc_xilinx_test1_a -format pdf -notitle test1
+show -prefix macc_xilinx_test2_a -format pdf -notitle test2
 
 techmap -map macc_xilinx_swap_map.v;;
 
-show -prefix macc_xilinx_test_b -format pdf -notitle
+show -prefix macc_xilinx_test1_b -format pdf -notitle test1
+show -prefix macc_xilinx_test2_b -format pdf -notitle test2
 
 techmap -map macc_xilinx_wrap_map.v
 
 connwrappers -unsigned $__mul_wrapper Y Y_WIDTH \
              -unsigned $__add_wrapper Y Y_WIDTH;;
 
-show -prefix macc_xilinx_test_c -format pdf -notitle
+show -prefix macc_xilinx_test1_c -format pdf -notitle test1
+show -prefix macc_xilinx_test2_c -format pdf -notitle test2
+
+design -push
+read_verilog macc_xilinx_xmap.v
+techmap -map macc_xilinx_swap_map.v
+techmap -map macc_xilinx_wrap_map.v;;
+design -save __macc_xilinx_xmap
+design -pop
+
+extract -constports -ignore_parameters \
+        -map %__macc_xilinx_xmap       \
+        -swap $__add_wrapper A,B ;;
+
+show -prefix macc_xilinx_test1_d -format pdf -notitle test1
+show -prefix macc_xilinx_test2_d -format pdf -notitle test2
+
+techmap -map macc_xilinx_unwrap_map.v;;
+
+show -prefix macc_xilinx_test1_e -format pdf -notitle test1
+show -prefix macc_xilinx_test2_e -format pdf -notitle test2
 
diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v b/manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
index 386635ac2..a80538d5b 100644
--- a/manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
@@ -7,9 +7,9 @@ parameter A_WIDTH = 1;
 parameter B_WIDTH = 1;
 parameter Y_WIDTH = 1;
 
-input [A_WIDTH-1:0] A;
-input [B_WIDTH-1:0] B;
-output [Y_WIDTH-1:0] Y;
+input [24:0] A;
+input [17:0] B;
+output [47:0] Y;
 
 wire [A_WIDTH-1:0] A_ORIG = A;
 wire [B_WIDTH-1:0] B_ORIG = B;
@@ -38,9 +38,9 @@ parameter A_WIDTH = 1;
 parameter B_WIDTH = 1;
 parameter Y_WIDTH = 1;
 
-input [A_WIDTH-1:0] A;
-input [B_WIDTH-1:0] B;
-output [Y_WIDTH-1:0] Y;
+input [47:0] A;
+input [47:0] B;
+output [47:0] Y;
 
 wire [A_WIDTH-1:0] A_ORIG = A;
 wire [B_WIDTH-1:0] B_ORIG = B;
diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_xmap.v b/manual/PRESENTATION_ExAdv/macc_xilinx_xmap.v
new file mode 100644
index 000000000..15bd04ed1
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/macc_xilinx_xmap.v
@@ -0,0 +1,10 @@
+module DSP48_MACC (a, b, c, y);
+
+input [24:0] a;
+input [17:0] b;
+input [47:0] c;
+output [47:0] y;
+
+assign y = a*b + c;
+
+endmodule