From: Oleg Endo Date: Sat, 25 Jul 2015 14:07:17 +0000 (+0000) Subject: re PR target/66930 (gengtype.c is miscompiled during stage2) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9354f9e7e2e50b1fd2527537e352404460bf77dd;p=gcc.git re PR target/66930 (gengtype.c is miscompiled during stage2) gcc/ PR target/66930 * config/sh/sh.c (sh_split_movrt_negc_to_movt_xor): Add missing T bit register modified_between_p check. From-SVN: r226218 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3178e2b6517..37b0ded42be 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2015-07-25 Oleg Endo + + PR target/66930 + * config/sh/sh.c (sh_split_movrt_negc_to_movt_xor): Add missing + T bit register modified_between_p check. + 2015-07-25 Uros Bizjak * config/i386/i386.c: Use SUBREG_P predicate. diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c index fe4cf4d64b8..f4291936fb1 100644 --- a/gcc/config/sh/sh.c +++ b/gcc/config/sh/sh.c @@ -13888,6 +13888,7 @@ sh_split_movrt_negc_to_movt_xor (rtx_insn* curr_insn, rtx operands[]) && !sh_insn_operands_modified_between_p (t_before_negc.insn, t_before_negc.insn, t_after_negc.insn) + && !modified_between_p (get_t_reg_rtx (), curr_insn, t_after_negc.insn) && !sh_unspec_insn_p (t_after_negc.insn) && !volatile_insn_p (PATTERN (t_after_negc.insn)) && !side_effects_p (PATTERN (t_after_negc.insn))