From: lkcl <lkcl@web>
Date: Mon, 5 Sep 2022 14:41:18 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~682
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=935902e81ea76691edeb64faabf322d4f0ae50b1;p=libreriscv.git

---

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 68dcd8dab..b5f78a1f0 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -60,7 +60,7 @@ Other modes are still applicable and include:
 * **Data-dependent fail-first**.
   useful to truncate VL based on
   analysis of a Condition Register result bit.
-* **Scalar and parallel reduction**.
+* **Reduction**.
   Reduction is useful
 for analysing a Vector of Condition Register Fields
 and reducing it to one
@@ -83,7 +83,6 @@ SVP64 RM `MODE` (includes `ELWIDTH_SRC` bits) for CR-based operations:
 | - | - |-------| --- |---------|----------------- |
 |sz |SNZ| 0 RG  |   0 | dz  /   | simple mode                      |
 |sz |SNZ| 0 RG  |   1 | 0   /   | scalar reduce mode (mapreduce), SUBVL=1 |
-|zz |SNZ| 0 RG  |   1 | 1   /   | parallel reduce mode (mapreduce), SUBVL=1 |
 |zz |SNZ| 0 RG  |   1 | SVM 0   | subvector reduce mode, SUBVL>1   |
 |zz |SNZ| 0 RG  |   1 | SVM 1   | Pack/Unpack mode, SUBVL>1   |
 |zz |SNZ| 1 VLI | inv |  CR-bit | Ffirst 3-bit mode      |