From: Steve Reinhardt Date: Thu, 18 May 2006 02:08:44 +0000 (-0400) Subject: Get basic full-system working with AtomicSimpleCPU. X-Git-Tag: m5_2.0_beta1~79 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=935ba67b4fbe595c0496e0230e39cd8ed87b7543;p=gem5.git Get basic full-system working with AtomicSimpleCPU. SConscript: Comment out sinic for now... needs to be fixed to compile under newmem. configs/test/SysPaths.py: Fix paths. configs/test/fs.py: SimpleCPU -> AtomicSimpleCPU Fix vmlinux path cpu/simple/atomic.cc: Fix suspendContext() so quiesce works. Don't forget to checkForInterrupts(). cpu/simple/base.cc: Minor fix to interrupt check code. dev/ide_disk.hh: Don't declare regStats() in header since it's not in .cc file anymore (will need to add it back in when stats are added back). dev/io_device.cc: Set packet dest to Packet::Broadcast. dev/pciconfigall.cc: Set PCI config packet result to Success. python/m5/objects/Root.py: Add debug object to Root so things like break_cycles can be set from command line. --HG-- extra : convert_revision : aa1c652fe589784e753e13ad9acb0cd5f3b6eafb --- diff --git a/SConscript b/SConscript index a2d5de279..4cc232bfd 100644 --- a/SConscript +++ b/SConscript @@ -207,7 +207,6 @@ full_system_sources = Split(''' dev/platform.cc dev/simconsole.cc dev/simple_disk.cc - dev/sinic.cc dev/tsunami.cc dev/tsunami_cchip.cc dev/tsunami_io.cc @@ -228,6 +227,7 @@ full_system_sources = Split(''' sim/pseudo_inst.cc ''') +# dev/sinic.cc if env['TARGET_ISA'] == 'alpha': diff --git a/configs/test/SysPaths.py b/configs/test/SysPaths.py index 7f231916c..c7c7db4e7 100644 --- a/configs/test/SysPaths.py +++ b/configs/test/SysPaths.py @@ -22,11 +22,11 @@ BINDIR = SYSTEMDIR + '/binaries' DISKDIR = SYSTEMDIR + '/disks' def disk(file): - return '%s/%s' % (DISKDIR, file) + return os.path.join(DISKDIR, file) def binary(file): - return '%s/%s' % (BINDIR, file) + return os.path.join(BINDIR, file) def script(file): - return '%s/%s' % ('/z/saidi/work/m5.newmem/configs/boot', file) + return os.path.join(SYSTEMDIR, 'boot', file) diff --git a/configs/test/fs.py b/configs/test/fs.py index ce121bd76..fdbf86abe 100644 --- a/configs/test/fs.py +++ b/configs/test/fs.py @@ -181,9 +181,9 @@ class LinuxAlphaSystem(LinuxAlphaSystem): read_only=True) simple_disk = SimpleDisk(disk=Parent.raw_image) intrctrl = IntrControl() - cpu = SimpleCPU(mem=Parent.magicbus2) + cpu = AtomicSimpleCPU(mem=Parent.magicbus2) sim_console = SimConsole(listener=ConsoleListener(port=3456)) - kernel = '/z/saidi/work/m5.newmem/build/vmlinux' + kernel = binary('vmlinux') pal = binary('ts_osfpal') console = binary('console') boot_osflags = 'root=/dev/hda1 console=ttyS0' diff --git a/cpu/simple/atomic.cc b/cpu/simple/atomic.cc index 8c38fe0d4..35a69cd4a 100644 --- a/cpu/simple/atomic.cc +++ b/cpu/simple/atomic.cc @@ -100,6 +100,9 @@ AtomicSimpleCPU::CpuPort::recvFunctional(Packet &pkt) void AtomicSimpleCPU::CpuPort::recvStatusChange(Status status) { + if (status == RangeChange) + return; + panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!"); } @@ -227,10 +230,13 @@ AtomicSimpleCPU::suspendContext(int thread_num) assert(cpuXC); assert(_status == Running); - assert(tickEvent.scheduled()); + + // tick event may not be scheduled if this gets called from inside + // an instruction's execution, e.g. "quiesce" + if (tickEvent.scheduled()) + tickEvent.deschedule(); notIdleFraction--; - tickEvent.deschedule(); _status = Idle; } @@ -417,6 +423,8 @@ AtomicSimpleCPU::tick() for (int i = 0; i < width; ++i) { numCycles++; + checkForInterrupts(); + ifetch_req->resetMin(); ifetch_pkt->reset(); Fault fault = setupFetchPacket(ifetch_pkt); @@ -452,7 +460,8 @@ AtomicSimpleCPU::tick() advancePC(fault); } - tickEvent.schedule(curTick + latency); + if (_status != Idle) + tickEvent.schedule(curTick + latency); } diff --git a/cpu/simple/base.cc b/cpu/simple/base.cc index 40868e74d..30c002ed5 100644 --- a/cpu/simple/base.cc +++ b/cpu/simple/base.cc @@ -307,8 +307,7 @@ void BaseSimpleCPU::checkForInterrupts() { #if FULL_SYSTEM - if (checkInterrupts && check_interrupts() && !cpuXC->inPalMode() && - status() != IcacheAccessComplete) { + if (checkInterrupts && check_interrupts() && !cpuXC->inPalMode()) { int ipl = 0; int summary = 0; checkInterrupts = false; diff --git a/dev/ide_disk.hh b/dev/ide_disk.hh index 891c462b5..2d04ecd09 100644 --- a/dev/ide_disk.hh +++ b/dev/ide_disk.hh @@ -259,12 +259,6 @@ class IdeDisk : public SimObject */ void reset(int id); - /** - * Register statistics. - */ - void regStats(); - - /** * Set the controller for this device * @param c The IDE controller diff --git a/dev/io_device.cc b/dev/io_device.cc index 24f33d84d..aa411d132 100644 --- a/dev/io_device.cc +++ b/dev/io_device.cc @@ -160,8 +160,7 @@ DmaPort::dmaAction(Command cmd, Addr addr, int size, Event *event, basePkt.flags = 0; basePkt.coherence = NULL; basePkt.senderState = NULL; - basePkt.src = 0; - basePkt.dest = 0; + basePkt.dest = Packet::Broadcast; basePkt.cmd = cmd; basePkt.result = Unknown; basePkt.req = NULL; diff --git a/dev/pciconfigall.cc b/dev/pciconfigall.cc index dfb1d48f6..a8c742b07 100644 --- a/dev/pciconfigall.cc +++ b/dev/pciconfigall.cc @@ -165,6 +165,7 @@ PciConfigAll::write(Packet &pkt) default: panic("invalid pci config write size\n"); } + pkt.result = Success; return pioDelay; } diff --git a/python/m5/objects/Root.py b/python/m5/objects/Root.py index f51516098..205a93c76 100644 --- a/python/m5/objects/Root.py +++ b/python/m5/objects/Root.py @@ -3,6 +3,7 @@ from Serialize import Serialize from Statistics import Statistics from Trace import Trace from ExeTrace import ExecutionTrace +from Debug import Debug class Root(SimObject): type = 'Root' @@ -19,3 +20,4 @@ class Root(SimObject): trace = Trace() exetrace = ExecutionTrace() serialize = Serialize() + debug = Debug()