From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 26 Feb 2020 14:13:16 +0000 (+0100)
Subject: interconnect/axi: remove mode on AXIInterface (not used and breaking LiteDRAM tests)
X-Git-Tag: 24jan2021_ls180~631
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=935e4effd20841931fa38f9c7209d72c10d5c631;p=litex.git

interconnect/axi: remove mode on AXIInterface (not used and breaking LiteDRAM tests)
---

diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py
index 905ef586..534a0cca 100644
--- a/litex/soc/interconnect/axi.py
+++ b/litex/soc/interconnect/axi.py
@@ -56,7 +56,7 @@ def r_description(data_width, id_width):
     ]
 
 class AXIInterface(Record):
-    def __init__(self, data_width, address_width, mode="master", id_width=1, clock_domain="sys"):
+    def __init__(self, data_width, address_width, id_width=1, clock_domain="sys"):
         self.data_width    = data_width
         self.address_width = address_width
         self.id_width      = id_width