From: whitequark <cz@m-labs.hk>
Date: Mon, 24 Dec 2018 09:31:51 +0000 (+0000)
Subject: hdl.mem: allow omitting memory simulation logic.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=93653bb3139a5f5262177f9162c0f88564d3ded5;p=nmigen.git

hdl.mem: allow omitting memory simulation logic.

Trying to transform very large arrays is slow.
---

diff --git a/nmigen/hdl/mem.py b/nmigen/hdl/mem.py
index a4f6137..f000188 100644
--- a/nmigen/hdl/mem.py
+++ b/nmigen/hdl/mem.py
@@ -6,7 +6,7 @@ from .ir import Instance
 
 
 class Memory:
-    def __init__(self, width, depth, init=None, name=None):
+    def __init__(self, width, depth, init=None, name=None, simulate=True):
         if not isinstance(width, int) or width < 0:
             raise TypeError("Memory width must be a non-negative integer, not '{!r}'"
                             .format(width))
@@ -29,8 +29,9 @@ class Memory:
 
         # Array of signals for simulation.
         self._array = Array()
-        for addr in range(self.depth):
-            self._array.append(Signal(self.width, name="{}({})".format(name, addr)))
+        if simulate:
+            for addr in range(self.depth):
+                self._array.append(Signal(self.width, name="{}({})".format(name, addr)))
 
         self.init = init
 
@@ -45,7 +46,7 @@ class Memory:
             raise ValueError("Memory initialization value count exceed memory depth ({} > {})"
                              .format(len(self.init), self.depth))
 
-        for addr in range(self.depth):
+        for addr in range(len(self._array)):
             if addr < len(self._init):
                 self._array[addr].reset = self._init[addr]
             else: