From: lkcl <lkcl@web>
Date: Mon, 24 Apr 2023 19:35:11 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=937019a21e74a65733244241abcc3c4f1c913982;p=libreriscv.git

---

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index 2b39ae9d7..66e6a3dbe 100644
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -120,7 +120,7 @@ from different sources is as follows:
 The reasoning here is that the opportunity to set RT equal to the
 immediate `SVi+1` is sacrificed in favour of setting from CTR.
 
-## Unusual Rc=1 behaviour
+**Unusual Rc=1 behaviour**
 
 Normally, the return result from an instruction is in `RT`. With it
 being possible for `RT=0` to mean that `CTR` mode is to be read, some