From: Gabe Black <gabeblack@google.com>
Date: Wed, 16 Oct 2019 02:24:27 +0000 (-0700)
Subject: fastmodel: Implement reading vector registers with readVecReg.
X-Git-Tag: v19.0.0.0~305
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=93790eb6813fb6ec9328244cdb19ec30722d334a;p=gem5.git

fastmodel: Implement reading vector registers with readVecReg.

The n other flavors of vector reading functions and all the vector
writing functions are not implemented currently.

Change-Id: I0c25c3ba47c7e4072da3d28596f44f6073b6f609
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22117
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
---

diff --git a/src/arch/arm/fastmodel/iris/arm/thread_context.cc b/src/arch/arm/fastmodel/iris/arm/thread_context.cc
index 8933535b9..26597d771 100644
--- a/src/arch/arm/fastmodel/iris/arm/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/arm/thread_context.cc
@@ -40,7 +40,7 @@ ArmThreadContext::ArmThreadContext(
         iris::IrisConnectionInterface *iris_if,
         const std::string &iris_path) :
     ThreadContext(cpu, id, system, dtb, itb, iris_if, iris_path),
-    pcRscId(iris::IRIS_UINT64_MAX)
+    vecRegs(TheISA::NumVecRegs), pcRscId(iris::IRIS_UINT64_MAX)
 {}
 
 void
@@ -55,6 +55,8 @@ ArmThreadContext::initFromIrisInstance(const ResourceMap &resources)
 
     extractResourceMap(intReg32Ids, resources, intReg32IdxNameMap);
     extractResourceMap(intReg64Ids, resources, intReg64IdxNameMap);
+
+    extractResourceMap(vecRegIds, resources, vecRegIdxNameMap);
 }
 
 TheISA::PCState
@@ -130,6 +132,21 @@ ArmThreadContext::setIntReg(RegIndex reg_idx, uint64_t val)
         call().resource_write(_instId, result, intReg64Ids.at(reg_idx), val);
 }
 
+const ArmISA::VecRegContainer &
+ArmThreadContext::readVecReg(const RegId &reg_id) const
+{
+    const RegIndex idx = reg_id.index();
+    ArmISA::VecRegContainer &reg = vecRegs.at(idx);
+
+    iris::ResourceReadResult result;
+    call().resource_read(_instId, result, vecRegIds.at(idx));
+    size_t data_size = result.data.size() * (sizeof(*result.data.data()));
+    size_t size = std::min(data_size, reg.SIZE);
+    memcpy(reg.raw_ptr<void>(), (void *)result.data.data(), size);
+
+    return reg;
+}
+
 Iris::ThreadContext::IdxNameMap ArmThreadContext::miscRegIdxNameMap({
         { ArmISA::MISCREG_CPSR, "CPSR" },
         { ArmISA::MISCREG_SPSR, "SPSR" },
@@ -816,4 +833,15 @@ Iris::ThreadContext::IdxNameMap ArmThreadContext::intReg64IdxNameMap({
         { ArmISA::INTREG_SPX, "SP" },
 });
 
+Iris::ThreadContext::IdxNameMap ArmThreadContext::vecRegIdxNameMap({
+        { 0, "V0" }, { 1, "V1" }, { 2, "V2" }, { 3, "V3" },
+        { 4, "V4" }, { 5, "V5" }, { 6, "V6" }, { 7, "V7" },
+        { 8, "V8" }, { 9, "V9" }, { 10, "V10" }, { 11, "V11" },
+        { 12, "V12" }, { 13, "V13" }, { 14, "V14" }, { 15, "V15" },
+        { 16, "V16" }, { 17, "V17" }, { 18, "V18" }, { 19, "V19" },
+        { 20, "V20" }, { 21, "V21" }, { 22, "V22" }, { 23, "V23" },
+        { 24, "V24" }, { 25, "V25" }, { 26, "V26" }, { 27, "V27" },
+        { 28, "V28" }, { 29, "V29" }, { 30, "V30" }, { 31, "V31" }
+});
+
 } // namespace Iris
diff --git a/src/arch/arm/fastmodel/iris/arm/thread_context.hh b/src/arch/arm/fastmodel/iris/arm/thread_context.hh
index 889d27f80..77603711d 100644
--- a/src/arch/arm/fastmodel/iris/arm/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/arm/thread_context.hh
@@ -43,6 +43,11 @@ class ArmThreadContext : public Iris::ThreadContext
     static IdxNameMap miscRegIdxNameMap;
     static IdxNameMap intReg32IdxNameMap;
     static IdxNameMap intReg64IdxNameMap;
+    static IdxNameMap vecRegIdxNameMap;
+
+    // Temporary holding places for the vector reg accessors to return.
+    // These are not updated live, only when requested.
+    mutable std::vector<ArmISA::VecRegContainer> vecRegs;
 
   public:
     ArmThreadContext(::BaseCPU *cpu, int id, System *system,
@@ -62,6 +67,7 @@ class ArmThreadContext : public Iris::ThreadContext
 
     ResourceIds intReg32Ids;
     ResourceIds intReg64Ids;
+    ResourceIds vecRegIds;
 
     void setIntReg(RegIndex reg_idx, RegVal val) override;
     RegVal readIntReg(RegIndex reg_idx) const override;
@@ -70,6 +76,8 @@ class ArmThreadContext : public Iris::ThreadContext
     {
         panic("%s not implemented.", __FUNCTION__);
     }
+
+    const VecRegContainer &readVecReg(const RegId &reg) const override;
 };
 
 } // namespace Iris