From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 22 Apr 2019 03:57:08 +0000 (+0100)
Subject: add TODO comment, bug #71, replace PLRU with LFSR
X-Git-Tag: div_pipeline~2183
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=939f091e7ed70c424c1f928c8cca5ae670dd1702;p=soc.git

add TODO comment, bug #71, replace PLRU with LFSR
---

diff --git a/TLB/src/SetAssociativeCache.py b/TLB/src/SetAssociativeCache.py
index 20957b78..d2aa6f47 100644
--- a/TLB/src/SetAssociativeCache.py
+++ b/TLB/src/SetAssociativeCache.py
@@ -7,6 +7,10 @@ from nmigen.cli import main
 from nmigen.cli import verilog, rtlil
 
 from AddressEncoder import AddressEncoder
+
+# TODO: use a LFSR that advances continuously and picking the bottom
+# few bits from it to select which cache line to replace, instead of PLRU
+# http://bugs.libre-riscv.org/show_bug.cgi?id=71
 from plru import PLRU
 
 SA_NA = "00" # no action (none)