From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 28 Dec 2021 02:30:11 +0000 (+0000)
Subject: add misaligned mmu.bin test 5 notes: currently LoadStore1 does not
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=93a94cddab5483f840d0d2029d660e5655983c5f;p=soc.git

add misaligned mmu.bin test 5 notes: currently LoadStore1 does not
support misaligned LD/ST therefore a 0x600 exception is raised
where actually a page-table lookup over the boundary (into a second
PTE which does not exist) should result in a 0x300 (DAR) fault.

also took the opportunity to set align_intr when no-cache is requested
on dcbz
---

diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py
index a245ddbd..48502690 100644
--- a/src/soc/experiment/mmu.py
+++ b/src/soc/experiment/mmu.py
@@ -722,6 +722,16 @@ def dcache_get(dut):
              0x12010: 0x0a00010000000000, # page table
     }
 
+    # microwatt mmu.bin test 5.
+    # PRTBL must be set to 0x12000, PID to 1
+    mem = {
+             0x0: 0x000000, # to get mtspr prtbl working
+             0x13cf8: 0x86b10000000000c0, # leaf node
+             0x13d00: 0x0000000000000000, # invalid leaf node
+             0x10008: 0x0930010000000080, # directory node
+             0x12010: 0x0a00010000000000, # page table
+    }
+
     while not stop:
         while True: # wait for dc_valid
             if stop:
@@ -819,7 +829,13 @@ def mmu_sim(dut):
 
     #addr = 0x10000  # original test
     #addr = 0x124108  # microwatt mmu.bin test 2
-    addr = 0x10b0d8  # microwatt mmu.bin test 4
+    #addr = 0x10b0d8  # microwatt mmu.bin test 4
+    # these are a misalignment test. one load results in two actual
+    # lookups, one of which has a valid page table entry, the other
+    # does not.  we currently do not support misaligned in Loadstore1
+    # therefore these tests fail with an align_intr (0x600) at 0x39fffd
+    addr = 0x39fffd # microwatt mmu.bin test 5
+    addr = 0x3a0000 # microwatt mmu.bin test 5
 
     # MMU PTE request
     yield dut.l_in.load.eq(1)
diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py
index 6d081eec..1ecac0ad 100644
--- a/src/soc/fu/ldst/loadstore.py
+++ b/src/soc/fu/ldst/loadstore.py
@@ -143,21 +143,26 @@ class LoadStore1(PortInterfaceBase):
         m.d.comb += self.req.priv_mode.eq(~msr.pr) # not-problem  ==> priv
         m.d.comb += self.req.virt_mode.eq(msr.dr) # DR ==> virt
         m.d.comb += self.req.mode_32bit.eq(~msr.sf) # not-sixty-four ==> 32bit
-        m.d.comb += self.req.align_intr.eq(misalign)
         m.d.comb += self.req.dcbz.eq(is_dcbz)
+        # XXX TODO sort out misalignment, mmu test5 fails
+        m.d.comb += self.req.align_intr.eq(misalign)
 
         # m.d.comb += Display("set_wr_addr %i dcbz %i",addr,is_dcbz)
 
         # option to disable the cache entirely for write
         if self.disable_cache:
             m.d.comb += self.req.nc.eq(1)
+
+        # dcbz cannot do no-cache
+        with m.If(is_dcbz & self.req.nc):
+            m.d.comb += self.req.align_intr.eq(1)
+
         return None
 
     def set_rd_addr(self, m, addr, mask, misalign, msr):
         m.d.comb += self.d_valid.eq(1)
         m.d.comb += self.req.load.eq(1) # load operation
         m.d.comb += self.req.byte_sel.eq(mask)
-        m.d.comb += self.req.align_intr.eq(misalign)
         m.d.comb += self.req.raddr.eq(addr)
         m.d.comb += self.req.priv_mode.eq(~msr.pr) # not-problem  ==> priv
         m.d.comb += self.req.virt_mode.eq(msr.dr) # DR ==> virt
@@ -169,6 +174,8 @@ class LoadStore1(PortInterfaceBase):
         # option to disable the cache entirely for read
         if self.disable_cache:
             m.d.comb += self.req.nc.eq(1)
+        # XXX TODO sort out misalignment, mmu test5 fails
+        m.d.comb += self.req.align_intr.eq(misalign)
         return None #FIXME return value
 
     def set_wr_data(self, m, data, wen):