From: Michel Dänzer <michel.daenzer@amd.com>
Date: Thu, 2 Aug 2012 15:30:44 +0000 (+0200)
Subject: radeonsi: Handle TGSI DIV opcode.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=93b4f1f97ea961f09218c9cf7d928e499f267f58;p=mesa.git

radeonsi: Handle TGSI DIV opcode.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
---

diff --git a/src/gallium/drivers/radeon/SIInstructions.td b/src/gallium/drivers/radeon/SIInstructions.td
index 94748b67259..31b9e5ec1c0 100644
--- a/src/gallium/drivers/radeon/SIInstructions.td
+++ b/src/gallium/drivers/radeon/SIInstructions.td
@@ -1088,6 +1088,11 @@ def : Pat <
 /* XXX: We are using IEEE MUL, not the 0 * anything = 0 MUL, is this correct? */
 def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_F32_e32, VReg_32>;
 
+def : Pat <
+  (int_AMDGPU_div AllReg_32:$src0, AllReg_32:$src1),
+  (V_MUL_LEGACY_F32_e32 AllReg_32:$src0, (V_RCP_LEGACY_F32_e32 AllReg_32:$src1))
+>;
+
 /********** ================== **********/
 /**********   VOP3 Patterns    **********/
 /********** ================== **********/