From: Chung-Ju Wu <jasonwucj@gmail.com>
Date: Sun, 10 Feb 2019 09:00:43 +0000 (+0000)
Subject: [NDS32] Have nds32_spilt_doubleword to split POST_INC.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=93c75052c4b6b3754d9f868f849645ab5f7a0de2;p=gcc.git

[NDS32] Have nds32_spilt_doubleword to split POST_INC.

gcc/
	* config/nds32/nds32-md-auxiliary.c (nds32_spilt_doubleword): Support
	to split POST_INC.

From-SVN: r268738
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b43a6681584..44183354d8f 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2019-02-10  Chung-Ju Wu  <jasonwucj@gmail.com>
+
+	* config/nds32/nds32-md-auxiliary.c (nds32_spilt_doubleword): Support
+	to split POST_INC.
+
 2019-02-09  Jan Hubicka  <hubicka@ucw.cz>
 
 	* ipa-visibility.c (localize_node): Also do not localize
diff --git a/gcc/config/nds32/nds32-md-auxiliary.c b/gcc/config/nds32/nds32-md-auxiliary.c
index 1a9cda5fb19..3c510cf6500 100644
--- a/gcc/config/nds32/nds32-md-auxiliary.c
+++ b/gcc/config/nds32/nds32-md-auxiliary.c
@@ -3163,16 +3163,30 @@ nds32_spilt_doubleword (rtx *operands, bool load_p)
       /* generate low_part and high_part memory format:
 	   low_part:  (post_modify ((reg) (plus (reg) (const 4)))
 	   high_part: (post_modify ((reg) (plus (reg) (const -12))) */
-      low_part[mem] = gen_frame_mem (SImode,
-				     gen_rtx_POST_MODIFY (Pmode, sub_mem,
-							  gen_rtx_PLUS (Pmode,
-							  sub_mem,
-							  GEN_INT (4))));
-      high_part[mem] = gen_frame_mem (SImode,
-				      gen_rtx_POST_MODIFY (Pmode, sub_mem,
-							   gen_rtx_PLUS (Pmode,
-							   sub_mem,
-							   GEN_INT (-12))));
+      low_part[mem] = gen_rtx_MEM (SImode,
+				   gen_rtx_POST_MODIFY (Pmode, sub_mem,
+							gen_rtx_PLUS (Pmode,
+							sub_mem,
+							GEN_INT (4))));
+      high_part[mem] = gen_rtx_MEM (SImode,
+				    gen_rtx_POST_MODIFY (Pmode, sub_mem,
+							 gen_rtx_PLUS (Pmode,
+							 sub_mem,
+							 GEN_INT (-12))));
+    }
+  else if (GET_CODE (sub_mem) == POST_INC)
+    {
+      /* memory format is (post_inc (reg)),
+	 so that extract (reg) from the (post_inc (reg)) pattern.  */
+      sub_mem = XEXP (sub_mem, 0);
+
+      /* generate low_part and high_part memory format:
+	   low_part:  (post_inc (reg))
+	   high_part: (post_inc (reg)) */
+      low_part[mem] = gen_rtx_MEM (SImode,
+				   gen_rtx_POST_INC (Pmode, sub_mem));
+      high_part[mem] = gen_rtx_MEM (SImode,
+				    gen_rtx_POST_INC (Pmode, sub_mem));
     }
   else if (GET_CODE (sub_mem) == POST_MODIFY)
     {
@@ -3189,14 +3203,14 @@ nds32_spilt_doubleword (rtx *operands, bool load_p)
       /* Generate low_part and high_part memory format:
 	   low_part:  (post_modify ((reg) (plus (reg) (const)))
 	   high_part: ((plus (reg) (const 4))) */
-      low_part[mem] = gen_frame_mem (SImode,
-				     gen_rtx_POST_MODIFY (Pmode, post_mem,
-							  gen_rtx_PLUS (Pmode,
-							  post_mem,
-							  post_val)));
-      high_part[mem] = gen_frame_mem (SImode, plus_constant (Pmode,
-							     post_mem,
-							     4));
+      low_part[mem] = gen_rtx_MEM (SImode,
+				   gen_rtx_POST_MODIFY (Pmode, post_mem,
+							gen_rtx_PLUS (Pmode,
+							post_mem,
+							post_val)));
+      high_part[mem] = gen_rtx_MEM (SImode, plus_constant (Pmode,
+							   post_mem,
+							   4));
     }
   else
     {