From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 4 Sep 2019 23:59:57 +0000 (-0700)
Subject: Compute sigP properly
X-Git-Tag: working-ls180~1039^2~205
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=93d798272d027f15aa930766bc3f9553f448f5cf;p=yosys.git

Compute sigP properly
---

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 9b01c22ee..c45e92d6f 100644
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -189,7 +189,7 @@ code ffP sigP clock
 
 		clock = c;
 
-		sigP = port(ffP, \Q);
+		sigP.replace(port(ffP, \D), port(ffP, \Q));
 	}
 endcode