From: lkcl <lkcl@web>
Date: Tue, 14 Sep 2021 14:46:55 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~138
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=93dfdaf49f2104057c176df72bc95920addb8fd2;p=libreriscv.git

---

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index c69cce01d..415588659 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -5,6 +5,8 @@ Links:
 * <https://bugs.libre-soc.org/show_bug.cgi?id=687>
 * [[svp64]]
 * [[sv/branches]]
+* [[opnpower/isa/sprset]]
+* [[/openpower/isa/condition]]
 
 Condition Register Fields are only 4 bits wide: this presents some
 interesting conceptual challenges for SVP64, particularly with respect to element