From: whitequark <whitequark@whitequark.org>
Date: Fri, 10 Apr 2020 14:51:01 +0000 (+0000)
Subject: Merge pull request #1603 from whitequark/ice40-ram_style
X-Git-Tag: working-ls180~668
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=93ef516d919b40ace2099bc7586bfda8648f0757;p=yosys.git

Merge pull request #1603 from whitequark/ice40-ram_style

ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
---

93ef516d919b40ace2099bc7586bfda8648f0757
diff --cc passes/memory/memory_map.cc
index da0673c8f,8820d6d72..9d455f55b
--- a/passes/memory/memory_map.cc
+++ b/passes/memory/memory_map.cc
@@@ -98,10 -119,40 +119,40 @@@ struct MemoryMapWorke
  			return;
  		}
  
+ 		// check if attributes allow us to infer FFRAM for this cell
+ 		for (const auto &attr : attributes) {
+ 			if (cell->attributes.count(attr.first)) {
+ 				const auto &cell_attr = cell->attributes[attr.first];
+ 				if (attr.second.empty()) {
+ 					log("Not mapping memory cell %s in module %s (attribute %s is set).\n",
+ 							cell->name.c_str(), module->name.c_str(), attr.first.c_str());
+ 					return;
+ 				}
+ 
+ 				bool found = false;
+ 				for (auto &value : attr.second) {
+ 					if (map_case(cell_attr) == map_case(value)) {
+ 						found = true;
+ 						break;
+ 					}
+ 				}
+ 				if (!found) {
+ 					if (cell_attr.flags & RTLIL::CONST_FLAG_STRING) {
+ 						log("Not mapping memory cell %s in module %s (attribute %s is set to \"%s\").\n",
+ 								cell->name.c_str(), module->name.c_str(), attr.first.c_str(), cell_attr.decode_string().c_str());
+ 					} else {
+ 						log("Not mapping memory cell %s in module %s (attribute %s is set to %d).\n",
+ 								cell->name.c_str(), module->name.c_str(), attr.first.c_str(), cell_attr.as_int());
+ 					}
+ 					return;
+ 				}
+ 			}
+ 		}
+ 
  		// all write ports must share the same clock
 -		RTLIL::SigSpec clocks = cell->getPort("\\WR_CLK");
 -		RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"];
 -		RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"];
 +		RTLIL::SigSpec clocks = cell->getPort(ID::WR_CLK);
 +		RTLIL::Const clocks_pol = cell->parameters[ID::WR_CLK_POLARITY];
 +		RTLIL::Const clocks_en = cell->parameters[ID::WR_CLK_ENABLE];
  		clocks_pol.bits.resize(wr_ports);
  		clocks_en.bits.resize(wr_ports);
  		RTLIL::SigSpec refclock;