From: Yunsup Lee <yunsup@cs.berkeley.edu>
Date: Thu, 19 May 2011 18:45:23 +0000 (-0700)
Subject: [sim] change default hwvl
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=93f1d11a4f8bb6b00bbd6528684076f29afbcef1;p=riscv-isa-sim.git

[sim] change default hwvl
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 3548810..0bab83a 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -37,11 +37,11 @@ processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz)
   vecbanks = 0xff;
   vecbanks_count = 8;
   utidx = -1;
-  vlmax = 8;
+  vlmax = 32;
   vl = 0;
   nxfpr_bank = 256;
-  nxpr_use = 0;
-  nfpr_use = 0;
+  nxpr_use = 32;
+  nfpr_use = 32;
   for (int i=0; i<MAX_UTS; i++)
     uts[i] = NULL;