From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sun, 10 Oct 2021 08:01:45 +0000 (+0200)
Subject: Import module attributes from Verific
X-Git-Tag: yosys-0.11~48^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=93fbc9fba4400814a859a9d9bfb05b3b92500e31;p=yosys.git

Import module attributes from Verific
---

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 231003753..c03e16eb2 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -917,6 +917,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
 	} else {
 		log("Importing module %s.\n", RTLIL::id2cstr(module->name));
 	}
+	import_attributes(module->attributes, nl, nl);
 
 	SetIter si;
 	MapIter mi, mi2;