From: H.J. Lu Date: Wed, 2 Apr 2008 13:53:38 +0000 (+0000) Subject: i386.md (plogic): New. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=94237c92ef2182d07f68ee45fedf20b2afbe26ae;p=gcc.git i386.md (plogic): New. 2008-04-02 H.J. Lu * config/i386/i386.md (plogic): New. (plogicprefix): Likewise. * config/i386/mmx.md (mmx_3): New. (mmx_and3): Removed. (mmx_ior3): Likewise. (mmx_xor3): Likewise. * config/i386/sse.md (3): New. (*3): Likewise. (*3): Likewise. (3): Likewise. (*sse_3): Likewise. (*sse2_3): Likewise. (tf3): Likewise. (*tf3): Likewise. (and3): Likewise. (*and3): Likewise. (ior3): Removed. (*ior3): Likewise. (xor3): Likewise. (*xor3): Likewise. (*and3): Likewise. (*ior3): Likewise. (*xor3): Likewise. (and3): Likewise. (*sse_and3): Likewise. (*sse2_and3): Likewise. (andtf3): Likewise. (*andtf3): Likewise. (ior3): Likewise. (*sse_ior3): Likewise. (*sse2_ior3): Likewise. (iortf3): Likewise. (*iortf3): Likewise. (xor3): Likewise. (*sse_xor3): Likewise. (*sse2_xor3): Likewise. (xortf3): Likewise. (*xortf3): Likewise. From-SVN: r133837 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2bd5c04b214..721fe8c9470 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,46 @@ +2008-04-02 H.J. Lu + + * config/i386/i386.md (plogic): New. + (plogicprefix): Likewise. + + * config/i386/mmx.md (mmx_3): New. + (mmx_and3): Removed. + (mmx_ior3): Likewise. + (mmx_xor3): Likewise. + + * config/i386/sse.md (3): New. + (*3): Likewise. + (*3): Likewise. + (3): Likewise. + (*sse_3): Likewise. + (*sse2_3): Likewise. + (tf3): Likewise. + (*tf3): Likewise. + (and3): Likewise. + (*and3): Likewise. + (ior3): Removed. + (*ior3): Likewise. + (xor3): Likewise. + (*xor3): Likewise. + (*and3): Likewise. + (*ior3): Likewise. + (*xor3): Likewise. + (and3): Likewise. + (*sse_and3): Likewise. + (*sse2_and3): Likewise. + (andtf3): Likewise. + (*andtf3): Likewise. + (ior3): Likewise. + (*sse_ior3): Likewise. + (*sse2_ior3): Likewise. + (iortf3): Likewise. + (*iortf3): Likewise. + (xor3): Likewise. + (*sse_xor3): Likewise. + (*sse2_xor3): Likewise. + (xortf3): Likewise. + (*xortf3): Likewise. + 2008-04-02 Richard Guenther PR tree-optimization/14495 diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index a72e7725d83..e2d68bb8209 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -540,6 +540,12 @@ (define_code_attr maxminiprefix [(smax "maxs") (smin "mins") (umax "maxu") (umin "minu")]) (define_code_attr maxminfprefix [(smax "max") (smin "min")]) +;; Mapping of parallel logic operators +(define_code_iterator plogic [and ior xor]) + +;; Base name for insn mnemonic. +(define_code_attr plogicprefix [(and "and") (ior "or") (xor "xor")]) + ;; All single word integer modes. (define_mode_iterator SWI [QI HI SI (DI "TARGET_64BIT")]) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 63e9025b4e3..bfcddc6614b 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -791,16 +791,6 @@ ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(define_insn "mmx_and3" - [(set (match_operand:MMXMODEI 0 "register_operand" "=y") - (and:MMXMODEI - (match_operand:MMXMODEI 1 "nonimmediate_operand" "%0") - (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))] - "TARGET_MMX && ix86_binary_operator_ok (AND, mode, operands)" - "pand\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxadd") - (set_attr "mode" "DI")]) - (define_insn "mmx_nand3" [(set (match_operand:MMXMODEI 0 "register_operand" "=y") (and:MMXMODEI @@ -811,27 +801,16 @@ [(set_attr "type" "mmxadd") (set_attr "mode" "DI")]) -(define_insn "mmx_ior3" +(define_insn "mmx_3" [(set (match_operand:MMXMODEI 0 "register_operand" "=y") - (ior:MMXMODEI + (plogic:MMXMODEI (match_operand:MMXMODEI 1 "nonimmediate_operand" "%0") (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))] - "TARGET_MMX && ix86_binary_operator_ok (IOR, mode, operands)" - "por\t{%2, %0|%0, %2}" + "TARGET_MMX && ix86_binary_operator_ok (, mode, operands)" + "p\t{%2, %0|%0, %2}" [(set_attr "type" "mmxadd") (set_attr "mode" "DI")]) -(define_insn "mmx_xor3" - [(set (match_operand:MMXMODEI 0 "register_operand" "=y") - (xor:MMXMODEI - (match_operand:MMXMODEI 1 "nonimmediate_operand" "%0") - (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")))] - "TARGET_MMX && ix86_binary_operator_ok (XOR, mode, operands)" - "pxor\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxadd") - (set_attr "mode" "DI") - (set_attr "memory" "none")]) - ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Parallel integral element swizzling diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index e1f316b216d..2b1e7f249b1 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -839,25 +839,6 @@ ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(define_expand "and3" - [(set (match_operand:SSEMODEF2P 0 "register_operand" "") - (and:SSEMODEF2P - (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "") - (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))] - "SSE_VEC_FLOAT_MODE_P (mode)" - "ix86_fixup_binary_operands_no_copy (AND, mode, operands);") - -(define_insn "*and3" - [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") - (and:SSEMODEF2P - (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0") - (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))] - "SSE_VEC_FLOAT_MODE_P (mode) - && ix86_binary_operator_ok (AND, mode, operands)" - "andp\t{%2, %0|%0, %2}" - [(set_attr "type" "sselog") - (set_attr "mode" "")]) - (define_insn "_nand3" [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") (and:SSEMODEF2P @@ -869,41 +850,22 @@ [(set_attr "type" "sselog") (set_attr "mode" "")]) -(define_expand "ior3" - [(set (match_operand:SSEMODEF2P 0 "register_operand" "") - (ior:SSEMODEF2P - (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "") - (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))] - "SSE_VEC_FLOAT_MODE_P (mode)" - "ix86_fixup_binary_operands_no_copy (IOR, mode, operands);") - -(define_insn "*ior3" - [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") - (ior:SSEMODEF2P - (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0") - (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))] - "SSE_VEC_FLOAT_MODE_P (mode) - && ix86_binary_operator_ok (IOR, mode, operands)" - "orp\t{%2, %0|%0, %2}" - [(set_attr "type" "sselog") - (set_attr "mode" "")]) - -(define_expand "xor3" +(define_expand "3" [(set (match_operand:SSEMODEF2P 0 "register_operand" "") - (xor:SSEMODEF2P + (plogic:SSEMODEF2P (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "") (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))] "SSE_VEC_FLOAT_MODE_P (mode)" - "ix86_fixup_binary_operands_no_copy (XOR, mode, operands);") + "ix86_fixup_binary_operands_no_copy (, mode, operands);") -(define_insn "*xor3" +(define_insn "*3" [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x") - (xor:SSEMODEF2P + (plogic:SSEMODEF2P (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0") (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))] "SSE_VEC_FLOAT_MODE_P (mode) - && ix86_binary_operator_ok (XOR, mode, operands)" - "xorp\t{%2, %0|%0, %2}" + && ix86_binary_operator_ok (, mode, operands)" + "p\t{%2, %0|%0, %2}" [(set_attr "type" "sselog") (set_attr "mode" "")]) @@ -912,16 +874,6 @@ ;; allocation lossage. These patterns do not allow memory operands ;; because the native instructions read the full 128-bits. -(define_insn "*and3" - [(set (match_operand:MODEF 0 "register_operand" "=x") - (and:MODEF - (match_operand:MODEF 1 "register_operand" "0") - (match_operand:MODEF 2 "register_operand" "x")))] - "SSE_FLOAT_MODE_P (mode)" - "andp\t{%2, %0|%0, %2}" - [(set_attr "type" "sselog") - (set_attr "mode" "")]) - (define_insn "*nand3" [(set (match_operand:MODEF 0 "register_operand" "=x") (and:MODEF @@ -933,23 +885,13 @@ [(set_attr "type" "sselog") (set_attr "mode" "")]) -(define_insn "*ior3" - [(set (match_operand:MODEF 0 "register_operand" "=x") - (ior:MODEF - (match_operand:MODEF 1 "register_operand" "0") - (match_operand:MODEF 2 "register_operand" "x")))] - "SSE_FLOAT_MODE_P (mode)" - "orp\t{%2, %0|%0, %2}" - [(set_attr "type" "sselog") - (set_attr "mode" "")]) - -(define_insn "*xor3" +(define_insn "*3" [(set (match_operand:MODEF 0 "register_operand" "=x") - (xor:MODEF + (plogic:MODEF (match_operand:MODEF 1 "register_operand" "0") (match_operand:MODEF 2 "register_operand" "x")))] "SSE_FLOAT_MODE_P (mode)" - "xorp\t{%2, %0|%0, %2}" + "p\t{%2, %0|%0, %2}" [(set_attr "type" "sselog") (set_attr "mode" "")]) @@ -3820,35 +3762,6 @@ operands[2] = force_reg (mode, gen_rtx_CONST_VECTOR (mode, v)); }) -(define_expand "and3" - [(set (match_operand:SSEMODEI 0 "register_operand" "") - (and:SSEMODEI (match_operand:SSEMODEI 1 "nonimmediate_operand" "") - (match_operand:SSEMODEI 2 "nonimmediate_operand" "")))] - "TARGET_SSE" - "ix86_fixup_binary_operands_no_copy (AND, mode, operands);") - -(define_insn "*sse_and3" - [(set (match_operand:SSEMODEI 0 "register_operand" "=x") - (and:SSEMODEI - (match_operand:SSEMODEI 1 "nonimmediate_operand" "%0") - (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))] - "(TARGET_SSE && !TARGET_SSE2) - && ix86_binary_operator_ok (AND, mode, operands)" - "andps\t{%2, %0|%0, %2}" - [(set_attr "type" "sselog") - (set_attr "mode" "V4SF")]) - -(define_insn "*sse2_and3" - [(set (match_operand:SSEMODEI 0 "register_operand" "=x") - (and:SSEMODEI - (match_operand:SSEMODEI 1 "nonimmediate_operand" "%0") - (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE2 && ix86_binary_operator_ok (AND, mode, operands)" - "pand\t{%2, %0|%0, %2}" - [(set_attr "type" "sselog") - (set_attr "prefix_data16" "1") - (set_attr "mode" "TI")]) - (define_insn "*sse_nand3" [(set (match_operand:SSEMODEI 0 "register_operand" "=x") (and:SSEMODEI @@ -3870,24 +3783,6 @@ (set_attr "prefix_data16" "1") (set_attr "mode" "TI")]) -(define_expand "andtf3" - [(set (match_operand:TF 0 "register_operand" "") - (and:TF (match_operand:TF 1 "nonimmediate_operand" "") - (match_operand:TF 2 "nonimmediate_operand" "")))] - "TARGET_64BIT" - "ix86_fixup_binary_operands_no_copy (AND, TFmode, operands);") - -(define_insn "*andtf3" - [(set (match_operand:TF 0 "register_operand" "=x") - (and:TF - (match_operand:TF 1 "nonimmediate_operand" "%0") - (match_operand:TF 2 "nonimmediate_operand" "xm")))] - "TARGET_64BIT && ix86_binary_operator_ok (AND, TFmode, operands)" - "pand\t{%2, %0|%0, %2}" - [(set_attr "type" "sselog") - (set_attr "prefix_data16" "1") - (set_attr "mode" "TI")]) - (define_insn "*nandtf3" [(set (match_operand:TF 0 "register_operand" "=x") (and:TF @@ -3899,96 +3794,51 @@ (set_attr "prefix_data16" "1") (set_attr "mode" "TI")]) -(define_expand "ior3" +(define_expand "3" [(set (match_operand:SSEMODEI 0 "register_operand" "") - (ior:SSEMODEI (match_operand:SSEMODEI 1 "nonimmediate_operand" "") - (match_operand:SSEMODEI 2 "nonimmediate_operand" "")))] + (plogic:SSEMODEI + (match_operand:SSEMODEI 1 "nonimmediate_operand" "") + (match_operand:SSEMODEI 2 "nonimmediate_operand" "")))] "TARGET_SSE" - "ix86_fixup_binary_operands_no_copy (IOR, mode, operands);") + "ix86_fixup_binary_operands_no_copy (, mode, operands);") -(define_insn "*sse_ior3" +(define_insn "*sse_3" [(set (match_operand:SSEMODEI 0 "register_operand" "=x") - (ior:SSEMODEI + (plogic:SSEMODEI (match_operand:SSEMODEI 1 "nonimmediate_operand" "%0") (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))] "(TARGET_SSE && !TARGET_SSE2) - && ix86_binary_operator_ok (IOR, mode, operands)" - "orps\t{%2, %0|%0, %2}" - [(set_attr "type" "sselog") - (set_attr "mode" "V4SF")]) - -(define_insn "*sse2_ior3" - [(set (match_operand:SSEMODEI 0 "register_operand" "=x") - (ior:SSEMODEI - (match_operand:SSEMODEI 1 "nonimmediate_operand" "%0") - (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE2 && ix86_binary_operator_ok (IOR, mode, operands)" - "por\t{%2, %0|%0, %2}" - [(set_attr "type" "sselog") - (set_attr "prefix_data16" "1") - (set_attr "mode" "TI")]) - -(define_expand "iortf3" - [(set (match_operand:TF 0 "register_operand" "") - (ior:TF (match_operand:TF 1 "nonimmediate_operand" "") - (match_operand:TF 2 "nonimmediate_operand" "")))] - "TARGET_64BIT" - "ix86_fixup_binary_operands_no_copy (IOR, TFmode, operands);") - -(define_insn "*iortf3" - [(set (match_operand:TF 0 "register_operand" "=x") - (ior:TF - (match_operand:TF 1 "nonimmediate_operand" "%0") - (match_operand:TF 2 "nonimmediate_operand" "xm")))] - "TARGET_64BIT && ix86_binary_operator_ok (IOR, TFmode, operands)" - "por\t{%2, %0|%0, %2}" - [(set_attr "type" "sselog") - (set_attr "prefix_data16" "1") - (set_attr "mode" "TI")]) - -(define_expand "xor3" - [(set (match_operand:SSEMODEI 0 "register_operand" "") - (xor:SSEMODEI (match_operand:SSEMODEI 1 "nonimmediate_operand" "") - (match_operand:SSEMODEI 2 "nonimmediate_operand" "")))] - "TARGET_SSE" - "ix86_fixup_binary_operands_no_copy (XOR, mode, operands);") - -(define_insn "*sse_xor3" - [(set (match_operand:SSEMODEI 0 "register_operand" "=x") - (xor:SSEMODEI - (match_operand:SSEMODEI 1 "nonimmediate_operand" "%0") - (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))] - "(TARGET_SSE && !TARGET_SSE2) - && ix86_binary_operator_ok (XOR, mode, operands)" - "xorps\t{%2, %0|%0, %2}" + && ix86_binary_operator_ok (, mode, operands)" + "ps\t{%2, %0|%0, %2}" [(set_attr "type" "sselog") (set_attr "mode" "V4SF")]) -(define_insn "*sse2_xor3" +(define_insn "*sse2_3" [(set (match_operand:SSEMODEI 0 "register_operand" "=x") - (xor:SSEMODEI + (plogic:SSEMODEI (match_operand:SSEMODEI 1 "nonimmediate_operand" "%0") (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE2 && ix86_binary_operator_ok (XOR, mode, operands)" - "pxor\t{%2, %0|%0, %2}" + "TARGET_SSE2 && ix86_binary_operator_ok (, mode, operands)" + "p\t{%2, %0|%0, %2}" [(set_attr "type" "sselog") (set_attr "prefix_data16" "1") (set_attr "mode" "TI")]) -(define_expand "xortf3" +(define_expand "tf3" [(set (match_operand:TF 0 "register_operand" "") - (xor:TF (match_operand:TF 1 "nonimmediate_operand" "") - (match_operand:TF 2 "nonimmediate_operand" "")))] + (plogic:TF + (match_operand:TF 1 "nonimmediate_operand" "") + (match_operand:TF 2 "nonimmediate_operand" "")))] "TARGET_64BIT" - "ix86_fixup_binary_operands_no_copy (XOR, TFmode, operands);") + "ix86_fixup_binary_operands_no_copy (, TFmode, operands);") -(define_insn "*xortf3" +(define_insn "*tf3" [(set (match_operand:TF 0 "register_operand" "=x") - (xor:TF + (plogic:TF (match_operand:TF 1 "nonimmediate_operand" "%0") (match_operand:TF 2 "nonimmediate_operand" "xm")))] - "TARGET_64BIT && ix86_binary_operator_ok (XOR, TFmode, operands)" - "pxor\t{%2, %0|%0, %2}" + "TARGET_64BIT && ix86_binary_operator_ok (, TFmode, operands)" + "p\t{%2, %0|%0, %2}" [(set_attr "type" "sselog") (set_attr "prefix_data16" "1") (set_attr "mode" "TI")])