From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 7 Jun 2020 18:31:05 +0000 (+0100)
Subject: add extra args to ISA in branch test_pipe_caller
X-Git-Tag: div_pipeline~494
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=9436eef70f511e53b1edd4e014fa8c91025b829d;p=soc.git

add extra args to ISA in branch test_pipe_caller
---

diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py
index 99913dcb..199a5eba 100644
--- a/src/soc/fu/branch/test/test_pipe_caller.py
+++ b/src/soc/fu/branch/test/test_pipe_caller.py
@@ -181,7 +181,8 @@ class TestRunner(FHDLTestCase):
                 print(test.name)
                 program = test.program
                 self.subTest(test.name)
-                simulator = ISA(pdecode2, test.regs, test.sprs, test.cr)
+                simulator = ISA(pdecode2, test.regs, test.sprs, test.cr,
+                                test.mem, test.msr)
                 initial_cia = 0x2000
                 simulator.set_pc(initial_cia)
                 gen = program.generate_instructions()