From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 27 Feb 2022 19:50:33 +0000 (+0000)
Subject: bit_length is 1 more than needed: subtract 1 from XLEN first
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=943d9e55c15bee4419a3f6a47a980628059c0451;p=soc.git

bit_length is 1 more than needed: subtract 1 from XLEN first
---

diff --git a/src/soc/fu/shift_rot/main_stage.py b/src/soc/fu/shift_rot/main_stage.py
index df8b17c2..4f83a99d 100644
--- a/src/soc/fu/shift_rot/main_stage.py
+++ b/src/soc/fu/shift_rot/main_stage.py
@@ -49,7 +49,7 @@ class ShiftRotMainStage(PipeModBase):
             comb += bitwise_lut.inputs[1].eq(self.i.ra)
             comb += bitwise_lut.inputs[2].eq(self.i.rc)
             # 6 == log2(64) because we have 64-bit values
-            grev = GRev(log2_width=XLEN.bit_length())
+            grev = GRev(log2_width=(XLEN-1).bit_length())
             m.submodules.grev = grev
             with m.If(op.is_32bit):
                 # 32-bit, so input is lower 32-bits zero-extended